SM72445_15 Datasheet, PDF (12/20 Pages) Texas Instruments – SM72445 Programmable Maximum Power Point Tracking Controller With Adjustable PWM Frequency

SM72445
SNVS795 – MARCH 2012
www.ti.com
I2C CONFIGURATION REGISTERS
The operation of the SM72445 can be configured through its I2C interface. Complete register settings for I2C
lines are shown below.
reg0 Register Description
Bits
Field
55:40
RSVD
39:30
ADC6
29:20
ADC4
19:10
ADC2
9:0
ADC0
Reset Value
16'h0
10'h0
10'h0
10'h0
10'h0
R/W
Bit Field Description
R
Reserved for future use.
R
Analog Channel 6 (slew rate detection time constant,
see adc config worksheet)
R
Analog Channel 4 (iout_max: maximum allowed output
current)
R
Analog Channel 2 (operating mode, see adc_config
worksheet)
R
Analog Channel 0 (vout_max: maximum allowed output
voltage)
reg1 Register Description
Bits
Field
Reset Value
R/W
55:41
RSVD
15'h0
R
40
mppt_ok
1'h0
R
39:30
Vout
10'h0
R
29:20
Iout
10'h0
R
19:10
Vin
10'h0
R
9:0
Iin
10'h0
R
Bit Field Description
Reserved for future use.
Internal mppt_start signal (test only)
Voltage out
Current out
Voltage in
Current in
reg3 Register Description
Bits
Field
55:47
RSVD
46
overide_adcprog
45
44:43
42:40
RSVD
RSVD
A2_override
Reset Value
9'd0
1'b0
1'b0
2'd1
3'd0
39:30
29:20
19:17
16:14
13:5
4
3
2
1
0
iout_max
vout_max
tdoff
tdon
dc_open
pass_through_sel
pass_through_ma
nual
bb_reset
clk_oe_manual
Open Loop
operation
10'd1023
10'd1023
3'h3
3'h3
9'hFF
1'b0
1'b0
1'b0
1'b0
1'b0
R/W
Bit Field Description
R/W
Reserved
R/W
When set to 1'b1,the below overide registers used
instead of ADC
R/W
Reserved
R/W
Reserved
R/W
Register override alternative for the three MSBs of
ADC2 (bits [9–7]) when reg3[46] is set. This allows
frequency and panel mode configuration to be set
through I2C
R/W
Register override alternative when reg3[46] is set for
maximum current threshold instead of ADC ch4
R/W
Register override alternative when reg3[46] is set for
maximum voltage threshold instead of ADC ch0
R/W
Dead time Off Time
R/W
Dead time On time
R/W
Open loop duty cycle (test only)
R/W
Overrides PM pin 28 and use reg3[3]
R/W
Control Panel Mode when pass_through_sel bit is 1'b1
R/W
Soft reset
R/W
Enable the PLL clock to appear on pin 5
R/W
Open Loop operation (MPPT disabled, receives duty
cycle command from reg 3b13:5); set to 1 and then
assert & deassert bb_reset to put the device in
openloop (test only)
12
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