LP38852S-ADJ Datasheet, PDF (14/29 Pages) Texas Instruments – 1.5A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start

LP38852
SNVS482E – JANUARY 2007 – REVISED APRIL 2013
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REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when V_IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when V_BIAS is below the UVLO threshold, or when the
Enable pin is held low.
When V_BIAS is above the UVLO threshold, and the Enable pin is above the V_EN(ON) threshold, the control circuitry
is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the
control circuit will drive the gate of the pass element to the full V_BIAS potential when the output voltage begins to
fall. In this condition, reverse current will flow from the output pin to the input pin , limited only by the R_DS(ON) of
the pass element and the output to input voltage differential. Discharging an output capacitor up 1000 µF in this
manner will not damage the device as the current will rapidly decay. However, continuous reverse current should
be avoided.
SOFT-START
The LP38852 incorporates a Soft-Start function that reduces the start-up current surge into the output capacitor
(C_OUT) by allowing V_OUT to rise slowly to the final value. This is accomplished by controlling V_REF at the SS pin.
The soft-start timing capacitor (C_SS) is internally held to ground until both V_BIAS rises above the Under-Voltage
Lock-Out threshold (ULVO) and the Enable pin is higher than the V_EN(ON) threshold.
V_REF will rise at an RC rate defined by the internal resistance of the SS pin (r_SS), and the external capacitor
connected to the SS pin. This allows the output voltage to rise in a controlled manner until steady-state
regulation is achieved. Typically, five time constants are recommended to assure that the output voltage is
sufficiently close to the final steady-state value. During the soft-start time the output current can rise to the built-in
current limit.
Soft-Start Time = C_SS × r_SS × 5
(7)
Since the V_OUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ),
and V_OUT will require four additional time constants (4τ) to reach the final value (5τ) .
After achieving normal operation, should either V_BIAS fall below the ULVO threshold, or the Enable pin fall below
the V_EN(OFF) threshold, the device output will be disabled and the Soft-Start capacitor (C_SS) discharge circuit will
become active. The C_SS discharge circuit will remain active until V_BIAS falls to 500 mV (typical). When V_BIAS falls
below 500 mV (typical), the C_SS discharge circuit will cease to function due to a lack of sufficient biasing to the
control circuitry.
Since V_REF appears on the SS pin, any leakage through C_SS will cause V_REF to fall, and thus affect V_OUT. A
leakage of 50 nA (about 10 MΩ) through C_SS will cause V_OUT to be approximately 0.1% lower than nominal, while
a leakage of 500 nA (about 1 MΩ) will cause V_OUT to be approximately 1% lower than nominal. Typical ceramic
capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient
temperature must be included in the capacitor selection process.
Typical C_SS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs
to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100
nF will provide soft-start, but may not be fully discharged if V_BIAS falls from the UVLVO threshold to less than 500
mV in less than 100 µs.
Figure 32 shows the relationship between the C_OUT value and a typical C_SS value.
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