CDCL1810 Datasheet, PDF (14/25 Pages) Texas Instruments – 1.8V, 10 Output, High-Performance Clock Distributor

CDCL1810
SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007
Table 1. Divide Ratio Settings for Post-Divider P0 or P1
Divide
Ratio
1
2
4
5
8
10
16
20
32
40
80
SELP1[3] or
SELP0[3]
0
0
0
0
0
0
0
0
1
1
1
SELP1[2] or
SELP0[2]
0
0
0
0
1
1
1
1
0
0
0
SELP1[1] or
SELP0[1]
0
0
1
1
0
0
1
1
0
0
1
SELP1[0] or
SELP0[0]
0
1
0
1
0
1
0
1
0
1
0
Notes
Default
Table 2. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80
Divide
Ratio
5
10
20
40
With PH0[4:0] = 00000
PH1
[4] [3] [2] [1] [0]
XX
X
X
X
XX
X
0
X
XX
X
1
X
XX
0
0
X
XX
0
1
X
XX
1
0
X
XX
1
1
X
X0
0
0
X
X0
0
1
X
X0
1
0
X
X0
1
1
X
X1
0
0
X
X1
0
1
X
X1
1
0
X
X1
1
1
X
Phase Lead
(radian)
0
0
(2π/2)
0
(2π/4)
2(2π/4)
3(2π/4)
0
(2π/8)
2(2π/8)
3(2π/8)
4(2π/8)
5(2π/8)
6(2π/8)
7(2π/8)
Phase setting not available
Notes
www.ti.com
14
Submit Documentation Feedback