SM320F28335-EP Datasheet, PDF (138/169 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581C – JUNE 2009 – REVISED JANUARY 2010
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t_dis(XD)XRNW
Table 6-39. External Interface Write Switching Characteristics (continued)
PARAMETER
MIN
Maximum time for DSP to release the data bus after XR/W inactive high
MAX UNIT
4 ns
(A) (B)
Lead
Active
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
(D)
XWE0, XWE1
XR/W
XD[0:31], XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XZCSH)}
t_{d(XCOH-XRNWL)}
t_d(XWEL-XD)
t_en(XD)XWEL
t_{d(XCOHL-XWEL)}
DOUT
t_{d(XCOHL-XWEH)}
t_{d(XCOHL-XRNWH)}
t_dis(XD)XRNW
t_h(XD)XWEH
(E)
XREADY
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-25. Example Write Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE XRDTRAIL USEREADY X2TIMING
N/A ⁽¹⁾
N/A ⁽¹⁾
N/A ⁽¹⁾
0
0
XWRLEAD
≥1
(1) N/A = Not applicable (or “Don’t care”) for this example
XWRACTIVE
≥0
XWRTRAIL
≥0
READYMODE
N/A ⁽¹⁾
138 Electrical Specifications
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