TPS54320 Datasheet, PDF (13/39 Pages) Texas Instruments – 4.5V to 17V Input 3A Synchronous Step Down SWIFT Converter

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TPS54320
SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010
Adjustable Switching Frequency and Synchronization (RT/CLK)
The RT/CLK pin can be used to set the switching frequency of the device in two modes.
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of
the device is adjustable from 200 kHz to 1200 kHz by using a maximum of 240 kΩ and minimum of 40.2 kΩ
respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized
to the external clock frequency with a PLL.
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch
from the RT mode to CLK mode.
Adjustable Switching Frequency (RT Mode)
To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 20. To
reduce the solution size, one would set the switching frequency as high as possible, but tradeoffs of the supply
efficiency and minimum controllable on time should be considered.
Rrt(kW) = 60281×Fsw (kHz)^-1.033
(4)
250
200
150
100
50
0
200 300 400 500 600 700 800 900 1000 1100 1200
Fsw - Oscillator Frequency - kHz
Figure 20. RT Set Resistor vs Switching Frequency
Synchronization (CLK mode)
An internal Phase Locked Loop (PLL) has been implemented to allow synchronization between 200kHz and
1.2MHz, and to easily switch from RT mode to CLK mode.
To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty
cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8V and higher than 2.0V.
The start of the switching cycle is synchronized to the falling edge of RT/CLK pin.
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Figure 21. Before the external clock is present, the device works in RT mode and the switching frequency is set
by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the
SYNC pin is pulled above the RT/CLK high threshold (2.0V), the device switches from the RT mode to the CLK
mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external
clock. It is not recommended to switch from the CLK mode back to the RT mode, because the internal switching
frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.
Copyright © 2010, Texas Instruments Incorporated
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