OPA330_15 Datasheet, PDF (13/37 Pages) Texas Instruments – 50μV VOS, 0.25μV/°C, 35μA CMOS OPERATIONAL AMPLIFIERS Zerø-Drift Series

www.ti.com
PHOTOSENSITIVITY
Although the OPA330 YFF package has a protective
backside coating that reduces the amount of light
exposure on the die, unless fully shielded, ambient
light can reach the active region of the device. Input
bias current for the package is specified in the
absence of light. Depending on the amount of light
exposure in a given application, an increase in bias
current, and possible increases in offset voltage
should be expected. Fluorescent lighting may
introduce noise or hum because of the time-varying
light output. Best layout practices include end-product
packaging that provides shielding from possible light
sources during operation.
QFN AND DFN PACKAGES
The OPA4330 is offered in a QFN package. The
OPA2330 is available in a DFN-8 package (also
known as SON), which is a QFN package with lead
contacts on only two sides of the bottom of the
package. These leadless, near-chip-scale packages
maximize board space and enhance thermal and
electrical characteristics through an exposed pad.
QFN and DFN packages are physically small, have a
smaller routing area, improved thermal performance,
and improved electrical parasitics, with a pinout
scheme that is consistent with other commonly-used
packages, such as SOIC and MSOP. Additionally, the
absence of external leads eliminates bent-lead
issues.
OPA330
OPA2330
OPA4330
SBOS432E – AUGUST 2008 – REVISED FEBRUARY 2011
The QFN and DFN package can be easily mounted
using standard PCB assembly techniques. See
Application Note QFN/SON PCB Attachment
(SLUA271) and Application Report Quad Flatpack
No-Lead Logic Packages (SCBA017), both available
for download at www.ti.com.
The exposed leadframe die pad on the bottom of
the package should be connected to V–.
QFN AND DFN LAYOUT GUIDELINES
The leadframe die pad should be soldered to a
thermal pad on the PCB. A mechanical data sheet
showing an example layout is attached at the end of
this data sheet. Refinements to this layout may be
required based on assembly process requirements.
Mechanical drawings located at the end of this data
sheet list the physical dimensions for the package
and pad. The five holes in the landing pattern are
optional, and are intended for use with thermal vias
that connect the leadframe die pad to the heatsink
area on the PCB.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests.
Even with applications that have low-power
dissipation, the exposed pad must be soldered to the
PCB to provide structural integrity and long-term
reliability.
© 2008–2011, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): OPA330 OPA2330 OPA4330