LP2951-50QDRGRQ1 Datasheet, PDF (13/24 Pages) Texas Instruments – ADJUSTABLE MICROPOWER VOLTAGE REGULATORS WITH SHUTDOWN

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APPLICATION INFORMATION
LP2951-33-Q1
LP2951-50-Q1
SLVSAW6D – JUNE 2011 – REVISED APRIL 2013
Input Capacitor (C_IN)
A 1-μF (tantalum, ceramic, or aluminum) electrolytic capacitor should be placed locally at the input of the
LP2951-xx-Q1 if there is, or will be, significant impedance between the ac filter capacitor and the input; for
example, if a battery is used as the input or if the ac filter capacitor is located more than 10 in away. There are
no ESR requirements for this capacitor, and the capacitance can be increased without limit.
Output Capacitor (C_OUT)
As with most PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and an
ESR that falls within a certain range.
Capacitance Value
For V_OUT ≥ 5 V, a minimum of 1 μF is required. For lower V_OUT, the regulator’s loop gain is running closer to unity
gain and, thus, has lower phase margins. Consequently, a larger capacitance is needed for stability. For V_OUT =
3.3 V, a minimum of 2.2 μF is recommended. For worst case, V_OUT = 1.23 V (using the ADJ version), a minimum
of 3.3 μF is recommended. C_OUT can be increased without limit and only improves the regulator stability and
transient response. Regardless of its value, the output capacitor should have a resonant frequency less than
500 kHz.
The minimum capacitance values given above are for maximum load current of 100 mA. If the maximum
expected load current is less than 100 mA, then lower values of C_OUT can be used. For instance, if I_OUT < 10 mA,
then only 0.33 μF is required for C_OUT. For I_OUT < 1 mA, 0.1 μF is sufficient for stability requirements. Thus, for a
worst-case condition of 100-mA load and V_OUT = V_REF = 1.235 V (representing the highest load current and
lowest loop gain), a minimum C_OUT of 3.3 μF is recommended.
The LP2951-xx-Q1 is used with external resistors to set the output voltage, a minimum load current of 1 μA is
recommended through the resistor divider.
ESR Range
The regulator control loop relies on the ESR of the output capacitor to provide a zero to add sufficient phase
margin to ensure unconditional regulator stability; this requires the closed-loop gain to intersect the open-loop
response in a region where the open-loop gain rolls off at 20 dB/decade. This ensures that the phase always is
less than 180° (phase margin greater than 0°) at unity gain. Thus, a minimum-maximum range for the ESR must
be observed.
The upper limit of this ESR range is established by the fact that too high an ESR could result in the zero
occurring too soon, causing the gain to roll off too slowly, which, in turn allows a third pole to appear before unity
gain and introduce enough phase shift to cause instability. This typically limits the max ESR to approximately
5 Ω.
Conversely, the lower limit of the ESR is tied to the fact that too low an ESR shifts the zero too far out (past unity
gain) and, thus, allows the gain to roll off at 40 dB/decade at unity gain, with a resulting phase shift of greater
than 180°. Typically, this limits the minimum ESR to approximately 20 mΩ to 30 mΩ.
For specific ESR requirements, see Typical Characteristics.
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