DRV591 Datasheet, PDF (13/16 Pages) Texas Instruments – 3-A HIGH-EFFICIENCY PWM POWER DRIVER

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For proper operation, the resistor R_OSC should have 1%
tolerance while capacitor C_OSC should be a ceramic type
with 10% tolerance. Both components should be grounded
to AGND, which should be connected to PGND at a single
point, typically where power and ground are physically
connected to the printed-circuit board.
EXTERNAL CLOCKING OPERATION
To synchronize the switching to an external clock signal,
pull the INT/EXT terminal low, and drive the clock signal
into the COSC terminal. This clock signal must be from
10% to 90% duty cycle and meet the voltage requirements
specified in the electrical specifications table. Since the
DRV591 includes an internal frequency doubler, the
external clock signal must be approximately 250 kHz.
Deviations from the 250 kHz clock frequency are allowed
and are specified in the electrical characteristic table. The
resistor connected from ROSC to ground may be omitted
from the circuit in this mode of operation—the source is
disconnected internally.
INPUT CONFIGURATION: DIFFERENTIAL
AND SINGLE-ENDED
If a differential input is used, it should be biased around the
midrail of the DRV591 and must not exceed the
common-mode input range of the input stage (see the
operating characteristics at the beginning of the data
sheet).
The most common configuration employs a single-ended
input. The unused input should be tied to V_DD/2, which
may be simply accomplished with a resistive voltage
divider. For the best performance, the resistor values
chosen should be at least 100 times lower than the input
resistance of the DRV591. This prevents the bias voltage
at the unused input from shifting when the signal input is
applied. A small ceramic capacitor should also be placed
from the input to ground to filter noise and keep the voltage
stable. An op amp configured as a buffer may also be used
to set the voltage at the unused input.
FIXED INTERNAL GAIN
The differential output voltage may be calculated using
equation (7):
ǒ Ǔ _{VO + VOUT)–VOUT– + Av VIN)–VIN–}
(7)
A_V is the voltage gain, which is fixed internally at 2.34 V/V.
The maximum and minimum ratings are provided in the
electrical specification table at the beginning of the data
sheet.
POWER SUPPLY DECOUPLING
To reduce the effects of high-frequency transients or
spikes, a small ceramic capacitor, typically 0.1 µF to 1 µF,
should be placed as close to each set of PVDD pins of the
DRV591
SLOS389A – NOVEMBER 2001– REVISED MAY 2002
DRV591 as possible. For bulk decoupling, a 10 µF to 100
µF tantalum or aluminum electrolytic capacitor should be
placed relatively close to the DRV591.
AREF CAPACITOR
The AREF terminal is the output of an internal mid-rail
voltage regulator used for the onboard oscillator and ramp
generator. The regulator may not be used to provide power
to any additional circuitry. A 1 µF ceramic capacitor must
be connected from AREF to AGND for stability (see
oscillator components above for AGND connection
information).
SHUTDOWN OPERATION
The DRV591 includes a shutdown mode that disables the
outputs and places the device in a low supply current state.
The SHUTDOWN pin may be controlled with a TTL logic
signal. When SHUTDOWN is held high, the device
operates normally. When SHUTDOWN is held low, the
device is placed in shutdown. The SHUTDOWN pin must
not be left floating. If the shutdown feature is unused, the
pin may be connected to VDD.
FAULT REPORTING
The DRV591 includes circuitry to sense three faults:
D Overcurrent
D Undervoltage
D Overtemperature
These three fault conditions are decoded via the FAULT1
and FAULT0 terminals. Internally, these are open-drain
outputs, so an external pull-up resistor of 5 kΩ or greater
is required.
Table 2. Fault Indicators
FAULT1
0
0
1
1
FAULT0
0
1
0
1
Overcurrent
Undervoltage
Overtemperature
Normal operation
The over-current fault is reported when the output current
exceeds four amps. As soon as the condition is sensed,
the over-current fault is set and the outputs go into a
high-impedance state for approximately 3 µs to 5 µs
(500 kHz operation). After 3 µs to 5 µs, the outputs are
re-enabled. If the over-current condition has ended, the
fault is cleared and the device resumes normal operation.
If the over-current condition still exists, the above
sequence repeats.
The under-voltage fault is reported when the operating
voltage is reduced below 2.8 V. This fault is not latched, so
as soon as the power-supply recovers, the fault is cleared
and normal operation resumes. During the under-voltage
condition, the outputs go into a high-impedance state
to prevent over-dissipation due to increased r_DS(on).
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