BQ24392-Q1_15 Datasheet, PDF (13/22 Pages) Texas Instruments – BQ24392-Q1 Dual SPST USB 2.0 High Speed Switch With USB Battery Charging Specification Revision 1.2 Detection

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10 Layout
BQ24392-Q1
SLIS160B – AUGUST 2014 – REVISED JANUARY 2015
10.1 Layout Guidelines
Place VBUS bypass capacitors as close to VBUS pin as possible and avoid placing the bypass caps near the
DP/DM traces.
The high speed DP/DM traces should always be matched lengths and must be no more than 4 inches;
otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a
shielded, twisted pair cable with a differential characteristic impedance of 90 Ω ±15%. In layout, the impedance
of DP and DM traces should match the cable characteristic differential 90-Ω impedance.
Route the high-speed USB signals using a minimum of vias and corners. This reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted pair
lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Due to high frequencies associated with the USB, a printed circuit board with at least four layers is
recommended; two signal layers separated by a ground and power layer as shown in Figure 8.
Figure 8. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer
should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or
power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing
the number of signal vias reduces EMI by reducing inductance at high frequencies.
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