ADS8361IDBQG4 Datasheet, PDF (13/29 Pages) Texas Instruments – Dual, 500kSPS, 16-Bit, 2 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER

Binary Two’s Complement
BTC
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
65535
65534
65533
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
32769
32768
32767
1000 0000 0000 0010
2
1000 0000 0000 0001
1
1000 0000 0000 0000
0
VNFS = V_CM – V_REF = 0V
0.000038V
0.000076V
0.000152V
2.499962V
2.500038V
VBPZ = 2.5V
Unipolar Analog Input Voltage
16-BIT
Bipolar Input, Binary Two’s Complement Output: (BTC)
Negative Full-Scale Code
Bipolar Zero Code
Positive Full-Scale Code
= VNFS = 8000_H, Vcode = V_CM – V_REF
= VBPZ = 0000_H, Vcode = V_CM
= VPFS = 7FFF_H, Vcode = (V_CM + V_REF) – 1LSB
VPFS = V_CM + V_REF = 5V
VPFS – 1LSB = 4.999924V
4.999848V
1LSB = 76μV
V_CM = 2.5V
V_REF = 2.5V
FIGURE 8. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX– = 2.5V, V_REF = 2.5V)
tion). Twenty clock cycles are required to perform a single
conversion. Immediately following CONVST switching to
HIGH, the ADS8361 will switch from the sample mode to the
hold mode asynchronous to the external clock. The BUSY
output pin will then go HIGH and remain HIGH for the
duration of the conversion cycle. On the falling edge of the
first cycle of the external clock, the ADS8361 will latch in the
address for the next conversion cycle depending on the
status of the A0 pin (HIGH = Channel 1, LOW = Channel 0).
The address must be selected 15ns prior to the falling edge of
cycle one of the external clock and must remain ‘held’ for 15ns
following the clock edge. For maximum throughput time, the
CONVST and RD pins should be tied together. CS must be
brought LOW to enable the CONVST and RD inputs. Data will
be valid on the falling edge of all 20 clock cycles per conver-
sion. The first bit of data will be a status flag for either Channel
0 or 1, the second bit will be a second status flag for either
Channel A or B. First and second bit will be 0 in Mode I. See
Table II below. The subsequent data will be MSB-first through
the LSB, followed by two zeros (see Table III and Figures 9
and 10).
MODE
M0
1
0
2
0
3
1
4
1
BIT 1
M1
0
1
0
1
TABLE II. Mode Selection.
BIT 2
CH0/1
0
0
0/1
0/1
CHA/B
0
0 = A/1 = B
0
0 = A/1 = B
CHANNEL SELECTION
Ch0/1 Selected by A0
Ch0/1 Selected by A0
Ch0/1 Alternating
Ch0/1 Alternating
DATA OUTPUT
On Data A and B
Sequentially on Data A
On Data A and B
Sequentially on Data A
CLOCK CYCLE
1
2
34 56
7 8 9 10 11 12 13 14 15 16 17 18 19 20
SERIAL DATA CH0 OR CH1 CHA OR CHB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0
TABLE III. Serial Data Output Format.
ADS8361
13
SBAS230E
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