TMS320F2810_08 Datasheet, PDF (126/173 Pages) Texas Instruments – Digital Signal Processors

Electrical Specifications
6.23 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6−28 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 6−28. Relationship Between Parameters Configured in XTIMING and Duration of Pulse^†‡
DESCRIPTION
X2TIMING = 0
DURATION (ns)
X2TIMING = 1
LR
Lead period, read access
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
AR
Active period, read access
(XRDACTIVE + WS + 1) × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
TR
Trail period, read access
XRDTRAIL × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
LW
Lead period, write access
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
AW
Active period, write access
(XWRACTIVE + WS + 1) × tc(XTIM) (XWRACTIVE × 2 + WS + 1) × tc(XTIM)
TW
Trail period, write access
XWRTRAIL × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
† _{tc(XTIM) − Cycle time, XTIMCLK}
‡ _{WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),}
then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
• If the XREADY signal is ignored (USEREADY = 0), then:
1. Lead:
LR ≥ t_c(XTIM)
LW ≥ t_c(XTIM)
These requirements result in the following XTIMING register configuration restrictions^§:
XRDLEAD
XRDACTIVE
XRDTRAIL
≥1
≥0
≥0
§ _{No hardware to detect illegal XTIMING configurations}
XWRLEAD
≥1
XWRACTIVE
≥0
XWRTRAIL
≥0
Examples of valid and invalid timing when not sampling XREADY^§:
XRDLEAD XRDACTIVE XRDTRAIL
Invalid
0
0
0
Valid
1
0
0
§ _{No hardware to detect illegal XTIMING configurations}
XWRLEAD
0
1
XWRACTIVE
0
0
XWRTRAIL
0
0
X2TIMING
0, 1
X2TIMING
0, 1
0, 1
April 2001 − Revised July 2007
SPRS174O 125