TSB12LV42 Datasheet, PDF (125/175 Pages) Texas Instruments – IEEE 1394-1995 Link-Layer Controller for Digital Video

BIT NUMBER
24
BIT NAME
CYCDONEEN
25
CYCPENDEN
26
CYCLOSTEN
27
CYCARBFLEN
28
ARBRSTGAPEN
29
SUBACTGAPEN
30
Not Used
31
ISOARBFLEN
DIR
FUNCTIONAL DESCRIPTION
R/W Cycle done interrupt enable. When set to a 1, the cycle done interrupt
status bit is enabled for generating an interrupt to the host processor.
R/W Cycle pending interrupt enable. When set to a 1, the cycle pending
interrupt status bit is enabled for generating an interrupt to the host
processor.
R/W Cycle lost interrupt enable. When set to a 1, the cycle lost interrupt
status bit is enabled for generating an interrupt to the host processor.
R/W Cycle arbitration failed interrupt enable. When set to a 1, the cycle
arbitration failed interrupt status bit is enabled for generating an
interrupt to the host processor.
R/W Arbitration reset gap interrupt enable. When set to a 1, the arbitration
reset gap interrupt status bit is enabled for generating an interrupt to the
host processor.
R/W Sub action gap interrupt enable. When set to a 1, the sub action gap
interrupt status bit is enabled for generating an interrupt to the host
processor.
R/W Isochronous arbitration failed interrupt enable. When set to a 1, the
isochronous arbitration failed interrupt status bit is enabled for
generating an interrupt to the host processor.
5.8 Extended Interrupt Register (EIR at Addr 018h)
The following register defines the group 1 interrupt status bits. With the exception of bits 1 and 2, the bits
in this register can be cleared 0 by writing a 1 to the bit. Unless otherwise specified the bits in this register
are defaulted to 0 on a power-up or software reset. With the exception of bit 1, the bits defined in this register
can be placed in a special test mode where the software can directly write to and/or read this register. This
is done by setting the REGRW bit in the link diagnostics register (DIAG at Addr 30h) to 1.
BIT NUMBER BIT NAME
DIR
FUNCTIONAL DESCRIPTION
00
Not Used
01
IGRP0
R Interrupt status bit flag. This bit is set to 1 whenever 1 or more interrupt
status bits register 1Ch or register 14h are set to 1.
02
IGRP1
R Interrupt status bit flag. When set to 1, one or more interrupt status bits in
this register are set to 1.
03
ARAV
R/W Asynchronous packet receive verification. When set to 1, a complete
asynchronous packet has been received into the asynchronous bulky
receive FIFO and the packet’s header information has been copied into
the Asynchronous Receive Packet Header registers.
04
IRAV
R/W Isochronous packet receive verification. When set to 1, a complete
isochronous packet has been received into the isochronous bulky receive
FIFO and the packet’s header information has been copied into the
isochronous receive packet header register.
05
Reserved
06
DRAV
R/W DV packet receive verification. When set to 1, a complete DV packet has
been received into the bulky data receive FIFO and the packet’s header
information has been copied into the receive packet header registers.
07
Reserved
5–13