TSB12LV42 Datasheet, PDF (118/175 Pages) Texas Instruments – IEEE 1394-1995 Link-Layer Controller for Digital Video

5.2 Version Register (VERS at Addr 000h)
This address port provides the application software with the version number and revision number of the
DVLynx device. These numbers are hardwired in the logic of the device.
BIT NUMBER BIT NAME DIR
FUNCTIONAL DESCRIPTION
00 – 15
VER
R Version number. Hardwired value = CE04h
16 – 31
REV
R Revision Number. Hardwired value = 1394h
5.3 C Acknowledge Register (CACK at Addr 004h)
This register provides the application software with the last acknowledge that was received for an
asynchronous packet transmitted from the asynchronous transmit control FIFO. Unless otherwise specified
the bits in this register are cleared to 0 on power-up or software initiated reset.
BIT NUMBER BIT NAME DIR
FUNCTIONAL DESCRIPTION
00 – 22
Not Used
R
23 – 27
CATACK
R Asynchronous control transmit acknowledge. The acknowledge value
received from the link transmitter for a packet that was transmitted from the
asynchronous control transmit FIFO. These bits are normally read only. For
diagnostic reasons these bits can be written to by the application software by
setting the REGRW bit in the link diagnostics register (DIAG at Addr 30h) to 1.
The default value of CATACK is 00000b
CATACK[23]
CATACK[24:27]
0
Normal 1394 4 bit ack code.
1
0000 – No Ack received. Ack timeout
1
0001 – Ack pkt longer than 8 bits
1
0010 – Ack pkt shorter than 8 bit
28 – 30
Not Used
R
31
CACKVAL R CATACK new value. This bit is set to 1 to indicate that the value of
CATACK[23:37] has been updated with a new value. This bit is cleared to 0
when the application software reads this register to obtain the value of
CATACK and CACKVAL. This bit is normally read only. For diagnostic
reasons this bit can be written to by setting the REGRW bit in the Link
Diagnostics register (DIAG at Addr 30h) to a 1. The default value of CACKVAL
is 0.
5.4 B Acknowledge Register (BACK at Addr 008h)
This register provides the application software with the last acknowledge that was received for an
asynchronous packet transmitted from the asynchronous transmit bulky FIFO. Unless otherwise specified
the bits in this register are cleared to 0 on powerup or software-initiated reset.
5–6