AM3359_13 Datasheet, PDF (125/236 Pages) Texas Instruments – Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (MPUs)

AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717F – OCTOBER 2011 – REVISED APRIL 2013
Table 5-18. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see Figure 5-15)
NO.
PARAMETER
10 Mbps
MIN TYP
MAX
100 Mbps
MIN TYP
MAX
1000 Mbps
MIN TYP
1 t_c(TXC)
Cycle time, TXC
360
2 t_w(TXCH)
Pulse duration, TXC
high
160
440
36
240
16
44
7.2
24
3.6
3 t_w(TXCL)
Pulse duration, TXC low
160
4 t_t(TXC)
Transition time, TXC
240
16
0.75
24
3.6
0.75
UNIT
MAX
8.8 ns
4.4 ns
4.4 ns
0.75 ns
RGMII[x]_TCLK
1
4
2
3
4
Figure 5-15. RGMII[x]_TCLK Timing - RGMII Mode
Table 5-19. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see Figure 5-16)
NO.
PARAMETER
10 Mbps
100 Mbps
1000 Mbps
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
1
t_sk(TD-TXC)
TD to TXC output skew
-0.5
t_{sk(TX_CTL-TXC)}
TX_CTL to TXC output skew
-0.5
2
t_t(TD)
t_{t(TX_CTL)}
Transition time, TD
Transition time, TX_CTL
0.5 -0.5
0.5 -0.5
0.75
0.75
0.5 -0.5
0.5 -0.5
0.75
0.75
0.5
ns
0.5
0.75
ns
0.75
RGMII[x]_TCLK^(A)
RGMII[x]_TD[3:0]^(B)
1
1st Half-byte 2nd Half-byte
1
2
RGMII[x]_TCTL^(B)
TXEN
TXERR
A. The Ethernet MAC and switch implemented in the AM335x device supports internal delay mode, but timing closure
was not performed for this mode of operation. Therefore, the AM335x device does not support internal delay mode.
B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
Figure 5-16. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
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Peripheral Information and Timings 125
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