AM3359_13 Datasheet, PDF (1/236 Pages) Texas Instruments – Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (MPUs)

AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717F – OCTOBER 2011 – REVISED APRIL 2013
Sitara™ AM335x ARM^® Cortex™-A8 Microprocessors (MPUs)
Check for Samples: AM3359, AM3358
1 Device Summary
1.1 Features
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• Highlights
– Up to 1-GHz Sitara™ ARM^® Cortex™-A8
32‑Bit RISC Microprocessor
• NEON™ SIMD Coprocessor
• 32KB of L1 Instruction and 32KB Data
Cache with Single-Error Detection (parity)
– 32KB of L1 Data Cache with Single Error-
Detection (parity)
– 256KB of L2 Cache with Error Correcting
Code (ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
• 256KB of L2 Cache with Error Correcting
– Emulation and Debug
Code (ECC)
• JTAG
– mDDR(LPDDR), DDR2, DDR3, DDR3L
– Interrupt Controller (up to 128 interrupt
Support
requests)
– General-Purpose Memory Support (NAND,
• On-Chip Memory (Shared L3 RAM)
NOR, SRAM) Supporting Up to 16-bit ECC
– 64 KB of General-Purpose On-Chip Memory
– SGX530 3D Graphics Engine
Controller (OCMC) RAM
– LCD and Touchscreen Controller
– Accessible to all Masters
– Programmable Real-Time Unit and Industrial
– Supports Retention for Fast Wake-Up
Communication Subsystem (PRU-ICSS)
• External Memory Interfaces (EMIF)
– Real-Time Clock (RTC)
– mDDR(LPDDR), DDR2, DDR3, DDR3L
– Up to Two USB 2.0 High-Speed OTG Ports
Controller:
with Integrated PHY
• mDDR: 200-MHz Clock (400-MHz Data
– 10, 100, 1000 Ethernet Switch Supporting Up
Rate)
to Two Ports
• DDR2: 266-MHz Clock (532-MHz Data
– Serial Interfaces Including:
Rate)
• Two Controller Area Network Ports (CAN)
• DDR3: 400-MHz Clock (800-MHz Data
• Six UARTs, Two McASPs, Two McSPI,
Rate)
and Three I2C Ports
• DDR3L: 400-MHz Clock (800-MHz Data
– 12-Bit Successive Approximation Register
Rate)
(SAR) ADC
• 16-Bit Data Bus
– Up to Three 32-Bit Enhanced Capture
• 1 GB of Total Addressable Space
Modules (eCAP)
• Supports One x16 or Two x8 Memory
– Up to Three Enhanced High-Resolution PWM
Device Configurations
Modules (eHRPWM)
– General-Purpose Memory Controller (GPMC)
– Crypto Hardware Accelerators (AES, SHA,
PKA, RNG)
• Flexible 8-Bit and 16-Bit Asynchronous
Memory Interface with Up to seven Chip
Selects (NAND, NOR, Muxed-NOR, SRAM)
• MPU Subsystem
• Uses BCH Code to Support 4-Bit, 8-Bit, or
– Up to 1-GHz ARM^® Cortex™-A8 32-Bit RISC
16-Bit ECC
Microprocessor
• Uses Hamming Code to Support 1-Bit
– NEON™ SIMD Coprocessor
ECC
– 32KB of L1 Instruction Cache with Single-
– Error Locator Module (ELM)
Error Detection (parity)
• Used in Conjunction with the GPMC to
1
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Sitara, SmartReflex, DSP/BIOS, XDS are trademarks of Texas Instruments.
2
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3
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PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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