TMS320DM355_08 Datasheet, PDF (124/154 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463D – SEPTEMBER 2007 – REVISED FEBRUARY 2008
www.ti.com
Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK⁽¹⁾⁽²⁾ (see Figure 5-30)
NO.
PARAMETER
DM355
UNIT
MIN
MAX
17
t_c(VCLK)
Cycle time, VCLK
18
t_w(VCLKH)
Pulse duration, VCLK high
19
t_w(VCLKL)
Pulse duration, VCLK low
20
t_t(VCLK)
Transition time, VCLK
21 t_{d(VCLKINH-VCLKH)} Delay time, VCLKIN high to VCLK high
22 t_{d(VCLKINL-VCLKL)} Delay time, VCLKIN low to VCLK low
23
t_{d(VCLK-VCTLV)}
Delay time, VCLK edge to VCTL valid
24
t_{d(VCLK-VCTLIV)}
Delay time, VCLK edge to VCTL invalid
25
t_{d(VCLK-VDATAV)}
Delay time, VCLK edge to VDATA valid
26
t_{d(VCLK-VDATAIV)}
Delay time, VCLK edge to VDATA invalid
13.33
5.7
5.7
2
2
0
0
160 ns
ns
ns
3 ns
12 ns
12 ns
4 ns
ns
4 ns
ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2) VCLKIN = PCLK or EXTCLK. For timing specifications relating to PCLK, see Table 5-17, Timing Requirements for VPFE PCLK
Master/Slave Mode.
VCLKIN^(A)
21
22
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
VCTL^(B)
VDATA^(C)
17
23
25
19
18
24
20
20
26
A. VCLKIN = PCLK or EXTCLK
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:3], G[7:2], and B[7:3]
Figure 5-30. VPBE Control and Data Output Timing With Respect to VCLK
5.9.2.4 DAC and Video Buffer Electrical Data/Timing
The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer
configuration. In the DAC only configuration the internal video buffer is not used and an external video
buffer is attached to the DAC. In the DAC and video buffer configuration, the DAC and internal video
buffer are both used and a TV cable may be attached directly to the output of the video buffer. See
Figure 5-31 and Figure 5-32 for recommenced circuits for each configuration.
124 DM355 Peripheral Information and Electrical Specifications
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