TMS320DM355_08 Datasheet, PDF (118/154 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463D – SEPTEMBER 2007 – REVISED FEBRUARY 2008
5.9.1.4 VPFE Electrical Data/Timing
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Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode⁽¹⁾ (see Figure 5-23)
NO.
1
t_c(PCLK)
Cycle time, PCLK
H3A not used
H3A used
MIN
13.33 or P⁽²⁾
2P + 1
MAX
100
100
UNIT
ns
ns
2
t_w(PCLKH)
3
t_w(PCLKL)
4
t_t(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
5.7
ns
5.7
ns
3 ns
(1) P = 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 135 MHz, use P = 7.41 ns. See Section 3.5, Device
Clocking, for more information on the supported clock configurations of the DM355.
(2) Use whichever value is greater.
2
3
1
PCLK
4
4
Figure 5-23. VPFE PCLK Timing
Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24)
NO.
5
t_{su(CCDV-PCLK)}
Setup time, CCD valid before PCLK edge
6
t_h(PCLK-CCDV)
Hold time, CCD valid after PCLK edge
7
t_su(HDV-PCLK)
Setup time, HD valid before PCLK edge
8
t_h(PCLK-HDV)
Hold time, HD valid after PCLK edge
9
t_su(VDV-PCLK)
Setup time, VD valid before PCLK edge
10
t_h(PCLK-VDV)
Hold time, VD valid after PCLK edge
11
t_{su(C_WEV-PCLK)}
Setup time, C_WE valid before PCLK edge
12
t_{h(PCLK-C_WEV)}
Hold time, C_WE valid after PCLK edge
13 t_{su(C_FIELDV-PCLK)} Setup time, C_FIELD valid before PCLK edge
14 t_{h(PCLK-C_FIELDV)} Hold time, C_FIELD valid after PCLK edge
DM355
MIN
3
2
3
2
3
2
3
2
3
2
UNIT
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
118 DM355 Peripheral Information and Electrical Specifications
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