TMS320C5515_101 Datasheet, PDF (123/160 Pages) Texas Instruments – TMS320C5515 Fixed-Point Digital Signal Processor

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6.14.2 I2S Electrical Data/Timing
TMS320C5515
SPRS645A – JANUARY 2010 – REVISED MARCH 2010
Table 6-35. Timing Requirements for I2S [I/O = 3.3 V, 2.75 V, and 2.5 V]⁽¹⁾ (see Figure 6-28)
NO.
1
t_c(CLK)
Cycle time, I2S_CLK
MASTER
CV_DD = 1.05 V
MIN
MAX
40 or 2P⁽¹⁾
(2)
CV_DD = 1.3 V
MIN
MAX
40 or 2P⁽¹⁾
(2)
SLAVE
CV_DD = 1.05 V
MIN
MAX
CV_DD = 1.3 V
MIN
MAX
40 or 2P^{(1) (2)}
40 or 2P^{(1) (2)}
2
t_w(CLKH)
Pulse duration, I2S_CLK high
20
3
t_w(CLKL)
Pulse duration, I2S_CLK low
20
t_su(RXV-CLKH)
Setup time, I2S_RX valid before I2S CLK
high (CLKPOL = 0)
5
7
t_su(RXV-CLKL)
Setup time, I2S_RX valid before I2S_CLK
low (CLKPOL = 1)
5
t_h(CLKH-RXV)
Hold time, I2S_RX valid after I2S_CLK high
(CLKPOL = 0)
3
8
t_h(CLKL-RXV)
Hold time, I2S_RX valid after I2S_CLK low
(CLKPOL = 1)
3
t_su(FSV-CLKH)
Setup time, I2S_FS valid before I2S_CLK
high (CLKPOL = 0)
–
9
t_su(FSV-CLKL)
Setup time, I2S_FS valid before I2S_CLK
low (CLKPOL = 1)
–
t_h(CLKH-FSV)
Hold time, I2S_FS valid after I2S_CLK high
(CLKPOL = 0)
–
10
t_h(CLKL-FSV)
Hold time, I2S_FS valid after I2S_CLK low
(CLKPOL = 1)
–
20
20
20
20
20
20
5
5
5
5
5
5
3
3
3
3
3
3
–
15
15
–
15
15
–
t_w(CLKH) + 0.6 ⁽³⁾
t_w(CLKH) + 0.6⁽³⁾
–
t_w(CLKL) + 0.6⁽³⁾
t_w(CLKL) + 0.6⁽³⁾
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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