TPS62600 Datasheet, PDF (12/21 Pages) Texas Instruments – 500-mA, 6-MHz SYNCHRONOUS STEP-DOWN CONVERTER IN CHIP SCALE PACKAGING

TPS62600
TPS62601
SLVS678 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
DETAILED DESCRIPTION
OPERATION
The TPS6260x is a synchronous step-down converter typically operates at a regulated 6-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6260x converter
operates in power-save mode with pulse frequency modulation (PFM).
The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line
response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of
each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the
output voltage until the main comparator trips, then the control logic turns off the switch.
One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response
to change in V_O is essentially instantaneous, which explains the transient response. The absence of a traditional,
high-gain compensated linear loop means that the TPS6260x is inherently stable over a range of L and C_O.
The device integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. When the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The current limit in the N-channel MOSFET is important for small duty-cycle operation when the current in the
inductor does not decrease because of the P-channel MOSFET current limit delay, or because of start-up
conditions where the output voltage is low.
SWITCHING FREQUENCY
The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of
50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The
intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa.
6MHz by a frequency locked loop.
When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls
below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather
than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at
low duty cycles.
When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can
be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL).
This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation
delay, hence increasing the switching frequency.
POWER-SAVE MODE
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically, the switching losses are
minimized, and the device runs with a minimum quiescent current and maintaining high efficiency. The converter
positions the dc output voltage approximately 0.5% above the nominal output voltage under light load conditions.
This voltage positioning feature minimizes voltage drops caused by a sudden load step.
When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal
voltage. It ramps up the output voltage with a minimum of three pulses and goes into power-save mode when the
inductor current has returned to a zero steady state. As a consequence of the dynamic voltage positioning in the
power-save mode, the average output voltage is slightly higher than its nominal value in PWM mode. For a load
transient from light load to heavy load, the logic returns the regulated output voltage to nominal after 64
continuous cycles.
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