SN65LVDS32A Datasheet, PDF (12/14 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL RECEIVERS

SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
APPLICATION INFORMATION
abstract terminated failsafe
Differential data line receivers commonly have failsafe circuits to prevent the receiver from switching on input
noise. This can occur when the bus driver is turned off or the interconnecting cable is damaged or left floating.
This is generally solved with an external resistor network that applies a steady state bias voltage to the undriven
input pins. In addition to the cost of external components, this has the effect of lowering the input magnitude
thereby reducing the differential noise margin. Current Integrated solutions will not work in wired-OR or common
mode termininated bus applications. The terminated failsafe circuit works over its entire extended common
mode range and will ensure a known state regardless of the common mode signal present.
Main Receiver
A
+
B
_
Output
Buffer
R
Reset
Failsafe
Timer
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 11. Receiver with Terminated Failsafe
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