SN65LVDS32A Datasheet, PDF (1/14 Pages) Texas Instruments – HIGH-SPEED DIFFERENTIAL RECEIVERS

SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
D Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard for Signaling
Rates^† Up to 400 Mbps
D Operates With a Single 3.3 V Supply
D –2 V to 4.4 V Common-Mode Input Voltage
Range
D Differential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
D Integrated 110Ω Line Termination Resistors
Offered With the LVDT Series
D Propagation Delay Times 4 ns (typ)
D Open-Circuit and Terminated Fail Safe
Assures a High-Level Output With No Input
D Bus-Pin ESD Protection Exceeds 15 kV
HBM
D Outputs High-Impedance With V_CC < 1.5 V
D Power Dissipation <400 mW With Four
Receivers Switching at 200 MHz
D Available in Small-Outline Package With
1,27 mm Terminal Pitch
D Pin-Compatible With the AM26LS32,
MC3486, or uA9637
description
This family of differential line receivers offer
improved performance and features that imple-
ment the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS is defined in
the TIA/EIA-644 standard. This improved perfor-
mance represents the second generation of
receiver products for this standard providing a
better overall solution for the cabled environment.
The next generation family of products is an
extension to TI’s overall product portfolio and is
not necessarily a replacement for older LVDS
receivers.
Improved features include an input common-
mode voltage range 2 V wider than the minimum
required by the standard. This will allow longer
cable lengths by tripling the allowable ground
noise tolerance to 3 V between a driver and
receiver.
SN65LVDS32A
SN65LVDT32A
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
1B 1
1A 2
16 V_CC
15 4B
G
G
SN65LVDT32A
1Y 3 14 4A
ONLY (4 Places)
1A
G 4 13 4Y
1Y
2Y 5 12 G
1B
2A 6 11 3Y
2A
2B 7 10 3A
2Y
GND 8
9 3B
2B
3A
3Y
3B
4A
4Y
4B
SN65LVDS3486A
SN65LVDT3486A
D PACKAGE
Logic Diagram
(TOP VIEW)
(positive logic)
SN65LVDT3486A
1B 1
16 V_CC
ONLY (4 Places)
1A 2 15 4B
1A
1Y
1Y 3 14 4A
1B
1,2EN 4
13 4Y
1,2EN
2Y 5 12 3,4EN
2A
2Y
2A 6 11 3Y
2B
2B 7 10 3A
GND 8
9 3B
3A
3Y
3B
3,4EN
4A
4Y
4B
SN65LVDS9637A
SN65LVDT9637A
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
V_CC 1
8 1A
1Y 2
7 1B
1A
1Y
2Y 3
6 2A
1B
GND 4
5 2B
SN65LVDT9637A
ONLY
2A
2Y
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
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