NE555 Datasheet, PDF (12/15 Pages) NXP Semiconductors – Timer

NE555, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – D1669, SEPTEMBER 1973—REVISED FEBRUARY 1992
APPLICATION INFORMATION
frequency divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 17 illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur
during the timing cycle.
ÏÏÏÏÏ VCC = 5 V
RA = 1250 Ω
ÏÏÏÏÏ _{C = 0.02 µF}
ÏÏÏÏÏÏÏÏÏÏ ^{See Figure 9}
Input Voltage
Output Voltage
Capacitor Voltage
Time – 0.1 ms/div
Figure 17. Divide-By-Three Circuit Waveforms
pulse-width modulation
The operation of the timer may be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 illustrates the resulting output pulse-width modulation. While a sine-wave
modulation signal is illustrated, any wave shape could be used.
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