DRV8823-Q1_15 Datasheet, PDF (12/22 Pages) Texas Instruments – 4-BRIDGE SERIAL INTERFACE MOTOR DRIVER

DRV8823-Q1
SLVSBH2B – JUNE 2012 – REVISED JANUARY 2013
Data Format
Table 1. Motor 1 Command (Bridges A and B)
Bit
D15–
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
Name
ADDR
(= 0000)
BDECAY
B12
B11
B10 BPHASE BENBL ADECAY A12
A11
Reset
Value
x
0
0
0
0
0
0
0
0
0
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D2
D1
D0
A10 APHASE AENBL
0
0
0
Table 2. Motor 2 Command (Bridges C and D)
Bit
D15–
D12
D11
D10 D9
D8
D7
D6
D5
D4
D3
Name
ADDR
(= 0001)
DDECAY
D12
D11
D10 DPHASE DENBL CDECAY
C12
C11
Reset
Value
x
0
0
0
0
0
0
0
0
0
D2
D1
D0
C10 CPHASE CENBL
0
0
0
Serial Data Timing
SCS
SCLK
SDATA
See Note 1
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
See Note 2
SSTB
Note 1: Any amount of time is allowed between clocks, or groups of clocks, as long as SCS stays active. This allows
8- or 16-bit transfers.
Note 2: If more than 16 clock edges are presented while transferring data (while SCS is still high), data continues to
be shifted into the data register.
Figure 4. Serial Data Timing Diagram
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