BUF22821 Datasheet, PDF (12/25 Pages) Texas Instruments – Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory

BUF22821
SBOS399 – JUNE 2007
Parity Error Correction
The BUF22821 provides single-bit parity error
correction for data stored in the nonvolatile memory
to provide increased reliability of the nonvolatile
memory. Should a single bit of nonvolatile memory
for a channel fail, the BUF22821 corrects for it and
updates the appropriate DAC with the intended value
when its memory is acquired.
Should more than one bit of nonvolatile memory for a
channel fail, the BUF22821 does not correct for it,
and updates the appropriate DAC/V_COM with the
default value of 1000000000.
DIE_ID AND DIE_REV REGISTERS
The user can verify the presence of the BUF22821 in
the system by reading from address 111101. The
BUF22821 returns 0101100100100101 when read at
this address.
The user can also determine the die revision of the
BUF22821 by reading from register 111100. The
BUF22821 returns 0000000000000000 when a RevA
die is present. RevB would be designated by
0000000000000001 and so on.
READ/WRITE OPERATIONS
Read and write operations can be done for a single
DAC/V_COM or for multiple DACs/V_COMs. Writing to a
DAC/V_COM register differs from writing to the
nonvolatile memory. Bits D15–D14 of the most
significant byte of data determines if data are written
to the DAC/V_COM register or the nonvolatile memory.
Read/Write: DAC/V_COM Register (volatile memory)
The BUF22821 is able to read from a single
DAC/V_COM, or multiple DACs/V_COMs, or write to the
register of a single DAC/V_COM, or multiple
DACs/V_COMs in a single communication transaction.
DAC pointer addresses begin with 000000 (which
corresponds to OUT1) through 010111 (which
corresponds to OUT22).
Write commands are performed by setting the
read/write bit LOW. Setting the read/write bit HIGH
performs a read transaction.
Writing: DAC/V_COM Register (volatile memory)
To write to a single DAC/V_COM register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
3. Send a DAC/V_COM pointer address byte. Set
bit D7 = 0 and D6 = 0. Bits D5–D0 are the
DAC/V_COM address. Only addresses 000000
to 010111 are valid and are acknowledged;
see Table 5 for valid addresses.
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4. Send two bytes of data for the specified
register. Begin by sending the most significant
byte first (bits D15–D8, of which only bits D9
and D8 are used, and bits D15–D14 must not
be 01), followed by the least significant byte
(bits D7–D0). The register is updated after
receiving the second byte.
5. Send a STOP or START condition on the bus.
The BUF22821 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register is not updated. Updating the DAC/V_COM
register is not the same as updating the DAC/V_COM
output voltage; see the Output Latch section.
The process of updating multiple DAC/V_COM registers
begins the same as when updating a single register.
However, instead of sending a STOP condition after
writing the addressed register, the master continues
to send data for the next register. The BUF22821
automatically and sequentially steps through
subsequent registers as additional data are sent. The
process continues until all desired registers have
been updated or a STOP or START condition is
sent.
To write to multiple DAC/V_COM registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF22821 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer
address byte for whichever DAC/V_COM is the
first in the sequence of DACs/V_COMs to be
updated. The BUF22821 begins with this
DAC/V_COM and steps through subsequent
DACs/V_COMs in sequential order.
4. Send the bytes of data; begin by sending the
most significant byte (bits D15–D8, of which
only bits D9 and D8 have meaning, and bits
D15–D14 must not be 01), followed by the
least significant byte (bits D7–D0). The first
two bytes are for the DAC/V_COM addressed in
the previous step. The DAC/V_COM register is
automatically updated after receiving the
second byte. The next two bytes are for the
following DAC/V_COM. That DAC/V_COM register
is updated after receiving the fourth byte. This
process continues until the registers of all
following DACs/V_COMs have been updated.
5. Send a STOP or START condition on the bus.
The BUF22821 acknowledges each byte. To
terminate communication, send a STOP or START
condition on the bus. Only DAC registers that have
received both bytes of data are updated.
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