TMS320R2812 Datasheet, PDF (117/147 Pages) Texas Instruments – TMS320R2811, TMS320R2812 Digital Signal Processors

Electrical Specifications
6.24 External Interface Write Timing
Table 6−28. External Memory Interface Write Switching Characteristics
PARAMETER
MIN MAX UNIT
t_{d(XCOH-XZCSL)}
Delay time, XCLKOUT high to zone chip-select active low
1 ns
t_{d(XCOHL-XZCSH)}
Delay time, XCLKOUT high or low to zone chip-select inactive high
−2
3 ns
t_d(XCOH-XA)
Delay time, XCLKOUT high to address valid
2 ns
t_{d(XCOHL-XWEL)}
Delay time, XCLKOUT high/low to XWE low
2 ns
t_{d(XCOHL-XWEH)}
Delay time, XCLKOUT high/low to XWE high
2 ns
t_{d(XCOH-XRNWL)}
Delay time, XCLKOUT high to XR/W low
1 ns
t_{d(XCOHL-XRNWH)}
Delay time, XCLKOUT high/low to XR/W high
−2
1 ns
t_en(XD)XWEL
Enable time, data bus driven from XWE low
0
ns
t_d(XWEL-XD)
Delay time, data valid after XWE active low
4 ns
t_h(XA)XZCSH
t_h(XD)XWE
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
†
ns
TW−2^‡
ns
t_dis(XD)XRNW
Data bus disabled after XR/W inactive high
4
ns
† _{During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.}
‡ _{TW = Trail period, write access. See Table 6−24.}
Lead
Active
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XZCSH)}
t_{d(XCOH-XRNWL)}
t_d(XWEL-XD)
t_en(XD)XWEL
t_{d(XCOHL-XWEL)}
DOUT
t_{d(XCOHL-XWEH)}
t_{d(XCOHL-XRNWH)}
t_dis(XD)XRNW
t_h(XD)XWEH
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−27. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
N/A^†
N/A^†
N/A^†
† _{N/A = “Don’t care” for this example}
USEREADY
0
X2TIMING
0
XWRLEAD
≥1
XWRACTIVE
≥0
XWRTRAIL
≥0
READYMODE
N/A^†
June 2004
SPRS257 117