TMS320R2812 Datasheet, PDF (107/147 Pages) Texas Instruments – TMS320R2811, TMS320R2812 Digital Signal Processors

Table 6−21. SPI Master Mode External Timing (Clock Phase = 1)^†‡
NO.
1
t_c(SPC)M
t_w(SPCH)M
2^§
t_w(SPCL)M
t_w(SPCL)M
3^§
t_w(SPCH)M
t_{su(SIMO-SPCH)M}
6^§
t_{su(SIMO-SPCL)M}
t_{v(SPCH-SIMO)M}
7^§
t_{v(SPCL-SIMO)M}
t_{su(SOMI-SPCH)M}
10^§
t_{su(SOMI-SPCL)M}
t_{v(SPCH-SOMI)M}
11^§
t_{v(SPCL-SOMI)M}
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low
(clock polarity = 1)
Pulse duration, SPICLK low
(clock polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
Setup time, SPISIMO data
valid before SPICLK high
(clock polarity = 0)
Setup time, SPISIMO data
valid before SPICLK low
(clock polarity = 1)
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 0)
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 1)
Setup time, SPISOMI before
SPICLK high
(clock polarity = 0)
Setup time, SPISOMI before
SPICLK low
(clock polarity = 1)
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 0)
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 1)
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
MIN
MAX
4t_c(LCO)
128t_c(LCO)
0.5t_c(SPC)M −10
0.5t_c(SPC)M
0.5t_c(SPC)M −10
0.5t_c(SPC)M
0.5t_c(SPC)M −10
0.5t_c(SPC)M
0.5t_c(SPC)M −10
0.5t_c(SPC)M
0.5t_c(SPC)M −10
0.5t_c(SPC)M −10
0.5t_c(SPC)M −10
0.5t_c(SPC)M −10
0
0
0.25t_c(SPC)M −10
0.25t_c(SPC)M −10
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
MIN
5t_c(LCO)
MAX
UNIT
127t_c(LCO) ns
0.5t_c(SPC)M − 0.5t_{c (LCO)}−10
0.5t_c(SPC)M − 0.5t_{c (LCO)}−10
0.5t_c(SPC)M − 0.5t_c(LCO)
ns
0.5t_c(SPC)M − 0.5t_c(LCO)
0.5t_c(SPC)M + 0.5t_c(LCO) − 10
0.5t_c(SPC)M + 0.5t_c(LCO) −10
0.5t_c(SPC)M + 0.5t_c(LCO)
ns
0.5t_c(SPC)M + 0.5t_c(LCO)
0.5t_c(SPC)M − 10
ns
0.5t_c(SPC)M − 10
0.5t_c(SPC)M − 10
ns
0.5t_c(SPC)M −10
0
ns
0
0.5t_c(SPC)M −10
ns
0.5t_c(SPC)M −10
† _{The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.}
‡
t_c(SPC)
=
SPI
clock
cycle
time
=
LSPCLK
4
or
LSPCLK
(SPIBRR ) 1)
t_c(LCO) = LSPCLK cycle time
§ _{The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).}
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
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