AM3517 Datasheet, PDF (117/184 Pages) Texas Instruments – ARM Microprocessor

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AM3517/05 ARM Microprocessor
SPRS550 – OCTOBER 2009
Table 6-24. DQS and Dx Routing Specification^{(1) (2)}
No. Parameter
Min
Typ Max
Unit
Notes
1 Center to center DQS-DQSN spacing
2w
2 DQS E Skew Length Mismatch
3 Center to center DQS to other DDR2 trace spacing
4 DQS/Dx nominal trace length
5 Dx to DQS Skew Length Mismatch
6 Dx to Dx Skew Length Mismatch
7 Center to center Dx to other DDR2 trace spacing
25
Mils
4w
DQLM-50 DQLM DQLM+ Mils
50
100
Mils
100
Mils
4w
See Note ⁽³⁾
See Notes ⁽²⁾,
(4)
See Note ⁽⁴⁾
See Note ⁽⁴⁾
See Notes ⁽³⁾,
(5)
8 Center to Center Dx to other Dx trace spacing
3w
See Notes ⁽⁶⁾,
(3)
9 Dx/DQS E Skew Length Mismatch
100
Mils
See Note ⁽⁴⁾
(1) "Dx" indicates a data line.
(2) Series terminator, if used, should be located closest to DDR.
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(5) Dx's from other DQS domains are considered other DDR2 trace.
(6) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.
Figure 6-25 shows the routing for the SDRC_STRBENx net classes. Table 6-25 contains the routing
specification.
A1
T
T
AM3517/05
A1
Figure 6-25. SDRC_STRBENx Routing
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 117