TMS320F243_07 Datasheet, PDF (115/121 Pages) Texas Instruments – DSP CONTROLLERS

TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006
register file compilation (continued)
Table 23. Register File Compilation (Continued)
ADDR
BIT 15
BIT 7
D15
07427h
D7
D15
07428h
D7
D15
07429h
D7
0742Ah
to
0742Bh
0742Ch
0742Dh
0742Eh
—
T1PINT
ENA
—
—
—
—
0742Fh
07430h
07431h
07432h
to
0743Fh
—
T1PINT
FLAG
—
—
—
—
—
FF0Fh
—
0FFFFh
—
ISWS.1
BIT 14
BIT 6
D14
D6
D14
D6
D14
D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ISWS.0
BIT 13
BIT 12
BIT 11
BIT 10
BIT 5
BIT 4
BIT 3
BIT 2
CAPTURE UNIT REGISTERS (CONTINUED)
D13
D12
D11
D10
D5
D4
D3
D2
D13
D12
D11
D10
D5
D4
D3
D2
D13
D12
D11
D10
D5
D4
D3
D2
BIT 9
BIT 1
D9
D1
D9
D1
D9
D1
Illegal
EVENT MANAGER (EV) INTERRUPT CONTROL REGISTERS
T1OFINT
T1UFINT
—
—
—
ENA
ENA
CMP3INT
CMP2INT
CMP1INT
—
—
ENA
ENA
ENA
—
—
—
—
—
—
—
T2OFINT
ENA
T2UFINT
ENA
T2CINT
ENA
—
—
—
—
—
CAP3INT
CAP2INT
—
—
—
ENA
ENA
—
—
—
T1OFINT
FLAG
T1UFINT
FLAG
—
—
CMP3INT
FLAG
CMP2INT
FLAG
CMP1INT
FLAG
—
—
—
—
—
T2OFINT
T2UFINT
T2CINT
—
—
FLAG
FLAG
FLAG
—
—
—
—
—
CAP3INT
CAP2INT
—
—
—
FLAG
FLAG
Illegal
I/O MEMORY SPACE
FLASH CONTROL MODE REGISTER
—
—
—
—
—
—
—
—
WAIT-STATE GENERATOR CONTROL REGISTER
—
—
—
BVIS.1
DSWS.2
DSWS.1
DSWS.0
PSWS.2
—
—
BVIS.0
PSWS.1
BIT 8
BIT 0
D8
D0
D8
D0
D8
D0
REG
CAP1FBOT
CAP2FBOT
CAP3FBOT
T1CINT
ENA
PDPINT
ENA
—
T2PINT
ENA
—
CAP1INT
ENA
T1CINT
FLAG
PDPINT
FLAG
—
T2PINT
FLAG
—
CAP1INT
FLAG
EVIMRA
EVIMRB
EVIMRC
EVIFRA
EVIFRB
EVIFRC
—
FCMR
—
ISWS.2
PSWS.0
WSGR
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