TPIC46L01 Datasheet, PDF (11/19 Pages) Texas Instruments – 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
chipset performance under fault conditions
The TPIC46L01, TPIC46L02, TPIC46L03, and power FET array’s are designed for normal operation over a
battery-voltage range of 8 V to 24 V with load fault detection from 4.8 V to 34 V. The TPIC46L01, TPIC46L02,
and TPIC46L03 offer on-board fault detection to handle a variety of faults that may occur within a system. The
circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs.
Unused DRAIN0–DRAIN5 inputs must be connected to V_BAT through a pullup resistor to prevent false reporting
of open-load fault conditions. This circuitry detects the fault, shuts off the output to the FET, and reports the fault
to the microcontroller. The primary faults under consideration are:
1. Shorted-load
2. Open-load
3. Over-battery voltage shutdown
4. Under-battery voltage shutdown
NOTE:
On the TPIC46L01 and TPIC46L02, an undervoltage fault may be detected when V_CC and V_BAT are
applied to the device. The controller should initialize the fault register after power up to clear any
false fault reports.
shorted–load fault condition
The TPIC46L01 and TPIC46L02 monitor the drain voltage of each channel to detect shorted-load conditions.
The on-board deglitch timer starts running when the gate output to the power FET transitions from the off state
to the on state. The timer provides a 60-µs deglitch time, t_(STBFM), to allow the drain voltage to stabilize after
the power FET has been turned on. The deglitch time is only enabled for the first 60 µs after the FET has been
turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than the fault reference
voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch time, t_(STBDG), then
FLT flags the microcontroller that a fault condition exists and the gate output is automatically shut off
(TPIC46L01 and TPIC46L03) until the error condition has been corrected.
An overheating condition on the FET occurs when the controller continually tries to re-enable the output under
shorted-load fault conditions. When a shorted-load fault is detected while using the TPIC46L02, the gate output
is transitioned into a low-duty-cycle PWM signal to protect the FET from overheating. The PWM rate is defined
as t_(SB) and the pulse with is defined as t_w. It remains in this low-duty-cycle pulse state until the fault has been
corrected or until the controller disables the gate output.
The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition.
Fault bits 0–5 distinguish faults for each of the output channels. When a shorted-load condition occurs with the
TPIC46L01, the controller must disable and re-enable the channel to clear the fault register and fault flag. The
TPIC46L02 automatically retries the output and the fault clears after the fault condition has been corrected.
Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET is turned on
and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates below the
reference point set at U1. The output of U1 is low and a fault condition is not flagged.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
11