SN54ABT8245 Datasheet, PDF (11/25 Pages) Texas Instruments – SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS

SN54ABT8245, SN74ABT8245
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS
SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996
instruction-register opcode description
The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each
instruction.
Table 3. Instruction-Register Opcodes
BINARY CODE†
BIT 7 → BIT 0
MSB → LSB
SCOPE OPCODE
DESCRIPTION
SELECTED DATA
REGISTER
00000000
10000001
EXTEST/INTEST
BYPASS‡
Boundary scan
Bypass scan
Boundary scan
Bypass
10000010
SAMPLE/PRELOAD
Sample boundary
Boundary scan
00000011
10000100
00000101
INTEST/EXTEST
BYPASS‡
BYPASS‡
Boundary scan
Bypass scan
Bypass scan
Boundary scan
Bypass
Bypass
00000110
HIGHZ
Control boundary to high impedance
Bypass
10000111
10001000
CLAMP
BYPASS‡
Control boundary to 1/0
Bypass scan
Bypass
Bypass
00001001
RUNT
Boundary run test
Bypass
00001010
READBN
Boundary read
Boundary scan
10001011
READBT
Boundary read
Boundary scan
00001100
CELLTST
Boundary self test
Boundary scan
10001101
TOPHIP
Boundary toggle outputs
Bypass
10001110
SCANCN
Boundary-control register scan
Boundary control
00001111
SCANCT
Boundary-control register scan
Boundary control
All others
BYPASS
Bypass scan
Bypass
† _{Bit 7 is used to maintain even parity in the 8-bit instruction.}
‡ _{The BYPASS instruction is executed in lieu of a SCOPE ™ instruction that is not supported in the ’ABT8245.}
MODE
Test
Normal
Normal
Test
Normal
Normal
Modified test
Test
Normal
Test
Normal
Test
Normal
Test
Normal
Test
Normal
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned
into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into
the output BSCs is applied to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
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