SM34020APCM40 Datasheet, PDF (11/89 Pages) Texas Instruments – GRAPHICS SYSTEM PROCESSOR

SM34020APCM40
GRAPHICS SYSTEM PROCESSOR
SGLS361 − JULY 2006
video timing and screen refresh
Twenty-eight I/O registers are dedicated to video timing and screen refresh functions. The SM34020APCM40
can be configured to drive composite synchronization or separate synchronization displays.
In composite synchronization mode, the SM34020APCM40 can be set to extract VSYNC and HSYNC from an
external CSYNC or it can be used to generate CSYNC from separate VSYNC and HSYNC inputs. Internally,
the SM34020APCM40 can be set to preset the horizontal and vertical counts on receipt of an external
synchronization signal. This allows compensation for any combination of internal and external delays that occur
in the video synchronization process. The HCOUNT register is loaded from SETHCNT by an external HYSYNC,
VCOUNT is loaded from SETVCNT on an external VSYNC, and an external CSYNC loads both HCOUNT and
VCOUNT from SETHCNT and SETVCNT, respectively.
The SM34020APCM40 directly supports VRAMs by generating the serial-data-register transfer cycles
necessary to refresh the display. The memory locations from which the display information is taken, as well as
the number of horizontal scan lines displayed between serial-data-register transfer cycles, are programmable.
The SM34020APCM40 supports various display resolutions and either interlaced or noninterlaced video. The
SM34020APCM40 can optionally be programmed to synchronize to externally-generated synchronization
signals so that images created by the SM34020APCM40 can be superimposed upon images created externally.
The external synchronization mode can also be used to synchronize the video signals generated by two or more
SM34020APCM40s in a multiple SM34020APCM40 graphics system.
CPU control registers
Five of the I/O registers (CONVDP, CONVMP, CONVSP, CONTROL, and PSIZE) provide CPU control to
configure the SM34020APCM40 for operation with specific characteristics. These characteristics include
pitches for pixel transfers, window checking mode, Boolean or arithmetic pixel processing operation,
transparency mode, PIXBLT direction control, and pixel size.
interrupt interface registers
Two dedicated I/O registers (INTENB and INTPEND) monitor and mask interrupt requests to the
SM34020APCM40, including two externally generated interrupts and three internally generated interrupts. An
internal interrupt request can be generated on one of the following conditions:
D Window violation – an attempt has been made to write a pixel to a location inside or outside a specified
window boundary.
D Host interrupt – the host processor has set the interrupt request bit in the host control register.
D Display interrupt – a specified horizontal line in the frame has been displayed on the screen.
D Bus fault
D Single-step emulator
A nonmaskable interrupt occurs when the host processor sets a control bit in the host interface register (NMI
in HSTCTLH). The host-initiated interrupt is associated with a mode bit (NMIM in HSTCTLH) that enables and
disables saving of the processor state on the stack when the interrupt occurs. This is useful if the host uses the
host interrupt before releasing the SM34020APCM40 to execute instructions (that is, before the stack pointer
is initialized). A dedicated terminal controls the SM34020APCM40 reset function.
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