PCM2704C_15 Datasheet, PDF (11/47 Pages) Texas Instruments – PCM270xC Stereo Audio DAC With USB Interface, Single-Ended Headphone Output andS/PDIF Output

www.ti.com
PCM2704C, PCM2705C, PCM2706C, PCM2707C
SBFS036B – MAY 2015 – REVISED AUGUST 2015
7.7 Audio Interface Timing Characteristics
Load capacitance of LRCK, BCK, and DOUT is 20 pF. For timing diagrams, see Figure 1 and Figure 2.
MIN
t_(BCY)
BCK pulse cycle time
300
t_(BCH)
BCK pulse duration, high
100
t_(BCL)
BCK pulse duration, low
100
t_(BL)
LRCK delay time from BCK falling edge
–20
t_(BD)
DOUT delay time from BCK falling edge
–20
t_(LD)
DOUT delay time from LRCK edge
–20
t_(DS)
DIN setup time
20
t_(DH)
DIN hold time
20
MAX
40
40
40
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
7.8 Audio Clock Timing Characteristics
Load capacitance is 20 pF. For timing diagrams, see Figure 3.
t_(SLL), t_(SLH)
t_(SBL), t_(SBH)
LRCK delay time from SYSCK rising edge
BCK delay time from SYSCK rising edge
MIN
MAX
UNIT
–5
10
ns
–5
10
ns
7.9 External ROM Read Interface Timing Characteristics
For timing diagrams, see Figure 4.
ƒ_(CK)
t_(BUF)
t_(LOW)
t_(HI)
t_(RS-SU)
t_(S-HD)
t_(RS-HD)
t_(D-SU)
t_(D-HD)
t_(CK-R)
t_(CK-F)
t_(DT-R)
t_(DT-F)
t_(P-SU)
C_B
V_NH
CK clock frequency
Bus free time between a STOP and a START condition
Low period of the CK clock
High period of the CK clock
Setup time for START/repeated START condition
Hold time for START/repeated START condition
Data setup time
Data hold time
Rise time of CK signal
Fall time of CK signal
Rise time of DT signal
Fall time of DT signal
Setup time for STOP condition
Capacitive load for DT and CK lines
Noise margin at high level for each connected device (including hysteresis)
MIN
4.7
4.7
4
4.7
4
250
0
20 + 0.1 C_B
20 + 0.1 C_B
20 + 0.1 C_B
20 + 0.1 C_B
4
0.2 V_DD
MAX
100
900
1000
1000
1000
1000
400
UNIT
kHz
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
pF
V
Copyright © 2015, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Links: PCM2704C PCM2705C PCM2706C PCM2707C