AMC7832_15 Datasheet, PDF (11/72 Pages) Texas Instruments – AMC7832 12-Bit Analog Monitor and Control Solution with Multi-Channel ADC, Bipolar DACs, Temperature Sensor and GPIO Ports

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AMC7832
SLAS836 – MARCH 2014
Electrical Characteristics (continued)
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. AV_DD = DV_DD = +4.5 to +5.5-V, AV_CC = +12-V, AV_EE = -12-V, IOV_DD = +1.8 to +5.5-V, AGND =
DGND = 0-V, AVSS_A,B,C,D = 0-V (DAC groups in positive ranges) or -12-V (DAC groups in negative range), DAC output range
= 0 to 10-V for all groups, no load on the DACs, T_A = -40°C to +105°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
INTERNAL REFERENCE SPECIFICATIONS
INTERNAL REFERENCE (Internal reference not accessable)
Initial accuracy
Reference temp. coefficient⁽⁸⁾
REF_OUT[1-2] BUFFERS⁽⁹⁾
T_A = 25°C
2.4925 2.5 2.5075 V
12
35 ppm/°C
Reference buffer offset
Capacitive load stability
T_A = 25°C
±2.5 mV
100 pF
INTERNAL ADC REFERENCE BUFFER
Reference buffer offset
GENERAL SPECIFICATIONS
T_A = 25°C
±5 mV
DIGITAL LOGIC: GPIO
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_OL
Low-level output voltage
Input impedance
DIGITAL LOGIC: All Except GPIO
IOV_DD =+1.8 to +5.5-V
IOV_DD = +1.8-V
IOV_DD = +2.7 to +5.5-V
IOV_DD = +1.8-V, Iload = -2-mA
IOV_DD= +5.5-V, Iload = -5-mA
To IOV_DD
0.7×IOV_DD
V
0.45 V
0.3×IOV_DD V
0.4 V
0.4 V
48
kΩ
V_IH
High-level input voltage
V_IL
Low-level input voltage
V_OH
High-level output voltage
V_OL
Low-level output voltage
High-impedance leakage
IOV_DD = +1.8 to +5.5-V
IOV_DD = +1.8-V
IOV_DD = +2.7 to +5.5-V
Iload = -1-mA
Iload = +1-mA
0.7×IOV_DD
IOV_DD-0.4
V
0.45 V
0.3×IOV_DD V
V
0.4 V
±5 µA
High-impedance output capacitance
10
pF
TIMING REQUIREMENTS
Reset delay
Delay to normal operation from reset
100
250 µs
Power-down recovery time
70 µs
Clamp shutdown delay
Convert pulse width
C_L = 10nF
100
µs
20
ns
Reset pulse width
20
ns
POWER-SUPPLY REQUIREMENTS
I_AVDD
I_AVCC
I_AVSS
I_DVDD
I_IOVDD
AV_DD supply current
AV_CC supply current
AV_SS supply current
DV_DD supply current
IOV_DD supply current
Power consumption
No DAC load, all DACs at 800h code and
ADC at the fastest auto conversion rate
–10
160
10 mA
10 mA
mA
3 mA
15 µA
mW
(8) Not tested during production. Specified by design and characterization.
(9) Intended to drive the VRANGE_A,B,C,D inputs only. An external buffer amplifier with high impedance input is required to drive any
additional external load.
Copyright © 2014, Texas Instruments Incorporated
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