TMS320DM335_1 Datasheet, PDF (106/158 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM335
Digital Media System-on-Chip (DMSoC)
SPRS528A – JULY 2008 – REVISED AUGUST 2008
www.ti.com
5.6 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). There
are a total of 7 GPIO banks in the DM335, because the DM335 has 104 GPIOs.
The DM335 GPIO peripheral supports the following:
• Up to 104 3.3v GPIO pins, GPIO[103:0]
• Interrupts:
– Up to 10 unique GPIO[9:0] interrupts from Bank 0
– Up to 7 GPIO (bank aggregated) interrupt signals, one from each of the 7 banks of GPIOs
– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
• DMA events:
– Up to 10 unique GPIO DMA events from Bank 0
– Up to 7 GPIO (bank aggregated) DMA event signals, one from each of the 7 banks of GPIOs
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
For more detailed information on GPIOs, see the TMS320DM335 Digital Media System-on-Chip (DMSoC)
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRUFY8).
5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing
NO.
1
t_w(GPIH)
2
t_w(GPIL)
Table 5-10. Timing Requirements for GPIO Inputs (see Figure 5-12)
Pulse duration, GPIx high
Pulse duration, GPIx low
DM335
MIN MAX
52
52
UNIT
ns
ns
Table 5-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-12)
NO.
PARAMETER
DM335
UNIT
MIN MAX
3
t_w(GPOH)
4
t_w(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
26 ⁽¹⁾
ns
26 ⁽¹⁾
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
106 DM335 Peripheral Information and Electrical Specifications
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