TMS320VC5507 Datasheet, PDF (105/135 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timings
5.14.1 McBSP0 Timings
Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
Table 5−23. McBSP0 Timing Requirements^†
NO.
MC1
MC2
t_c(CKRX)
t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
CLKR/X ext
CV_DD = 1.2 V
CV_DD = 1.35 V
MIN MAX
2P^‡
P–1^‡
CV_DD = 1.6 V
MIN
2P^‡
P–1^‡
MAX
UNIT
ns
ns
MC3 t_r(CKRX)
Rise time, CLKR/X
CLKR/X ext
6
6 ns
MC4 t_f(CKRX)
MC5 t_su(FRH-CKRL)
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR int
CLKR ext
6
6 ns
10
7
ns
2
2
CLKR int
−3
MC6 t_h(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR ext
1
CLKR int
10
MC7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR ext
2
−3
ns
1
7
ns
2
MC8 t_h(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int
−2
CLKR ext
3
−2
ns
3
CLKX int
13
MC9 t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
3
8
ns
2
CLKX int
−3
MC10 t_h(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKX ext
1
−3
ns
1
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are}
also inverted.
‡ _{P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.}
April 2004 − Revised January 2005
SPRS244C 105