DP83849IVSX Datasheet, PDF (104/108 Pages) Texas Instruments – DP83849I PHYTER DUAL Industrial erature with Flexible Port Switching

8.2.29 Single Clock MII (SCMII) Receive Timing
PMD Input Pair ^{IDLE (J/K)}
X1
T2.29.3
CRS
RX_DV
RXD[1:0]
RX_ER
Data
T2.29.5
(TR)
Data
T2.29.4
T2.29.1
T2.29.2
T2.29.2
Parameter
Description
Notes
T2.29.1
X1 Clock Period
25MHz Reference Clock
T2.29.2
RXD[3:0], RX_DV and RX_ER From X1 rising
output delay
T2.29.3
CRS ON delay (100Mb)
100BASE-TX mode
T2.29.4
CRS OFF delay (100Mb)
100BASE-TX mode
T2.29.5
RXD[1:0] and RX_ER latency 100BASE-TX mode
(100Mb)
Min Typ Max Units
40
ns
2
18 ns
19
bits
26
bits
56
bits
Note: Output delays assume a 25pF load.
Note: CRS is asserted and deasserted asynchronously relative to the reference clock.
Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to assertion of CRS_DV.
Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to deassertion of
CRS_DV.
Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with
the Elasticity Buffer set to the default value (01).
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