AM1705_1007 Datasheet, PDF (103/156 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Table 6-58. General Timing Requirements for SPI1 Slave Modes ⁽¹⁾ (continued)
No.
14 t_{oh(SPC_SOMI)S}
15 t_{su(SIMO_SPC)S}
16 t_{ih(SPC_SIMO)S}
PARAMETER
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Output hold time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK falling
Input Setup Time,
SPI1_SIMO valid before
receive edge of SPI1_CLK
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK rising
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Input Hold Time, SPI1_SIMO
valid after receive edge of
SPI1_CLK
Polarity = 0, Phase = 1,
from SPI1_CLK rising
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
MIN
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0
0
0
0
5
5
5
5
MAX
UNIT
ns
ns
ns
Table 6-59. Additional⁽¹⁾ SPI1 Master Timings, 4-Pin Enable Option^{(2) (3)}
No.
17 t_{d(EN A_SPC)M}
18 t_{d(SPC_ENA)M}
PARAMETER
MIN
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Delay from slave assertion of SPI1_ENA
active to first SPI1_CLK from master.⁽⁴⁾
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK edge to
ensure master does not begin the next
transfer. ⁽⁵⁾
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MAX
UNIT
3P + 3
0.5t_c(SPC)M + 3P + 3
ns
3P + 3
0.5t_c(SPC)M + 3P + 3
0.5t_c(SPC)M + P + 5
P+5
ns
0.5t_c(SPC)M + P + 5
P+5
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-57 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
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Peripheral Information and Electrical Specifications 103
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