TPS65132_15 Datasheet, PDF (10/64 Pages) Texas Instruments – TPS65132 Single Inductor - Dual Output Power Supply

TPS65132
SLVSBM1G – JUNE 2013 – REVISED AUGUST 2015
www.ti.com
7.6 I²C Interface Timing Requirements / Characteristics ⁽¹⁾
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f_SCL SCL clock frequency
Standard mode
Fast mode
100 kHz
400 kHz
t_LOW LOW period of the SCL clock
Standard mode
4.7
µs
Fast mode
1.3
µs
t_HIGH HIGH period of the SCL clock
Standard mode
4.0
µs
Fast mode
600
ns
Standard mode
4.7
µs
t_BUF Bus free time between a STOP and START condition
Fast mode
1.3
µs
Standard mode
4.0
µs
t_hd;STA Hold time for a repeated START condition
Fast mode
600
ns
Standard mode
4.7
µs
t_su;STA Setup time for a repeated START condition
Fast mode
600
ns
t_su;DAT Data setup time
Standard mode
250
ns
Fast mode
100
ns
t_hd;DAT Data hold time
Standard mode
Fast mode
0.05
3.45 µs
0.05
0.9 µs
t_RCL1
Rise time of SCL signal after a repeated START condition
and after an acknowledge bit
t_RCL Rise time of SCL signal
t_FCL Fall time of SCL signal
t_RDA Rise time of SDA signal
t_FDA Fall time of SDA signal
t_su;STO Setup time for STOP condition
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
4.0
600
1000 ns
1000 ns
1000 ns
300 ns
300 ns
300 ns
1000 ns
300 ns
300 ns
300 ns
µs
ns
C_B
Capacitive load for SDA and SCL
0.4 nF
(1) Industry standard I²C timing characteristics acoording to I²C-Bus Specification, Version 2.1, January 2000. Not tested in production.
SDA
t_f
SCL
S
t_LOW
t_r
t_su;DAT
t_f
t_hd;STA
t_r
t_BUF
t_hd;STA
t_hd;DAT
HIGH
t_su;STA
Sr
t_su;STO
P
S
Figure 1. Serial Interface Timing For F/S-Mode
10
Submit Documentation Feedback
Product Folder Links: TPS65132
Copyright © 2013–2015, Texas Instruments Incorporated