TLV320AIC3106 Datasheet, PDF (10/99 Pages) Texas Instruments – LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

TLV320AIC3106
SLAS509A – DECEMBER 2006 – REVISED APRIL 2007
AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM
WCLK
BCLK
SDOUT
td^(DO-WS)
td^(WS)
td^(DO-BCLK)
SDIN
ts^(DI)
Figure 1. I²S/LJF/RJF Timing in Master Mode
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th^(DI)
TIMING CHARACTERISTICS⁽¹⁾
All specifications typical at 25°C, DVDD = 1.8 V
PARAMETER
t_d (WS)
t_d (DO-WS)
t_d (DO-BCLK)
t_s(DI)
t_h(DI)
t_r
t_f
ADWS/WCLK delay time
ADWS/WCLK to DOUT delay time
BCLK to DOUT delay time
DIN setup time
DIN hold time
Rise time
Fall time
(1) All timing specifications are measured at characterization but not tested at final test.
IOVDD = 1.1 V
MIN MAX
50
50
50
10
10
30
30
IOVDD = 3.3 V
MIN MAX
15
20
15
6
6
10
10
UNIT
ns
ns
ns
ns
ns
ns
ns
WCLK
BCLK
td^(WS)
td^(WS)
td^(DO-BCLK)
SDOUT
SDIN
ts^(DI)
Figure 2. DSP Timing in Master Mode
th^(DI)
10
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