TLC5930 Datasheet, PDF (10/39 Pages) Texas Instruments – 12-CHANNEL LED DRIVER

TLC5930
SLLS528 – MARCH 2002
PRINCIPLES OF OPERATION
packet operation
Data output is performed with delay of two bits from input. In other words, by using the edge of the input, data
before two bits appear in the output terminal. Figure 4 shows the concept for data transfer when some TLC5930s
are connected in a cascade, where data A–Z indicates valid data, and the asterisk (*) marks invalid data. Also,
data A is a first data input from controller, and there is assumed to be no data transition for DATA/STROBE
between [H and I] and [S and T] in the IC1 input data.
Invalid data is clocked out corresponding to the input edge to ensure that no data exists before data A. After
that, data A is clocked out with a time delay of two bits plus t_{D(D/STIN–D/STOUT)} using the input edge for data C.
Once data output is started, data before two bits from current input is sequentially clocked out using the input
edge. It should be noted that data output stays during no transition of DATA/STROBE, since no input edge
makes the output edge. Figure 4 shows that the output of IC1 remains in data F and does not go to data G until
the edge of input data I is entered (after IC1 clocked out data F, although the input data of IC1 is continued from
A to H.)
If data A to H are included in one packet, the data output for each output of the device in data H, (which indicates
the completion of packet operation), is performed out at the edge establishing data J for IC1, data L for IC2, data
O for IC3, and data Q for IC4 from the view of controller. In other words, in order to complete the packet operation
for all the devices connected in cascades, additional bit data equivalent to two times the number of devices
cascaded is needed to be clocked in.
Additionally, since each device has the time delay, T_{D(D/STIN–D/STOUT)}, from input to output, the controller views
that output having a time delay exceeding two bits against a virtual input to IC1. In this example, while, in
practice, the output data H for IC4 is established by the input edge of data Q, it appears to be synchronized with
data S for IC1.
ABCDE FGH
IC1 INPUT DATA
2 bit+tD(D/STIN_{–D/STOUT)}
I J K L M O PQR S T U VWX Y Z
tD(D/STIN_{–D/STOUT)}
IC2 INPUT DATA
IC1 OUTPUT DATA
* * ABCDEF
GH I J K LMOPQR S T U VWX
IC3 INPUT DATA
IC2 OUTPUT DATA
IC4 INPUT DATA
IC3 OUTPUT DATA
* * * * ABCD
* * * * * * AB
E F GH I J K LMOPQR S T U V
CD E F G H I J K LMO PQR S
IC4 OUTPUT DATA
2-bit + tD _{(D/STIN – D/STOUT)}
********
A BC D E F G H I J K L M O P Q
Figure 4. Data Transfer Concept in Cascade Connection
UDG–02032
10
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