DRV601_15 Datasheet, PDF (10/19 Pages) Texas Instruments – DIRECTPATH™ STEREO LINE DRIVER, ADJUSTABLE GAIN

DRV601
SLOS553C – JANUARY 2008 – REVISED SEPTEMBER 2009......................................................................................................................................... www.ti.com
SQUARE WAVE OUTPUT VOLTAGE
with
CAPACITIVE LOAD
t − Time = 20 ms/div
Figure 14.
Layout Recommendations
A proposed layout for the DRV601 can be seen in the DRV601EVM user's guide, SLOU215, and the Gerber files
can be downloaded on www.ti.com, open the DRV601 product folder and look in the Tools & Software folder.
Exposed Pad On DRV601RTJ Package
The exposed metal pad on the DRV601RTJ package must be soldered down to a pad on the PCB in order to
maintain reliability. The pad on the PCB should be allowed to float and not be connected to ground or power.
Connecting this pad to power or ground prevents the device from working properly because it is connected
internally to PVSS.
SGND and PGND Connections
The SGND and PGND pins of the DRV601 must be routed back to the decoupling capacitor separately in order
to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part
functions without risk of failure, but the noise and THD performance do not meet the specifications.
Gain setting resistors
The gain setting resistors, R_in and R_fb , must be placed close to pin 13 respectively pin 17 to minimize the
capacitive loading on these input pins and to ensure maximum stability of the DRV601. For the recommenced
PCB layout, see the DRV601EVM user guide.
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Product Folder Link(s): DRV601