BQ20Z75_08 Datasheet, PDF (10/20 Pages) Texas Instruments – SBS 1.1-COMPLIANT GAS GAUGE AND PROTECTION-ENABLED IC WITH IMPEDANCE TRACK

bq20z75
SLUS723C – JULY 2007 – REVISED JULY 2008............................................................................................................................................................... www.ti.com
SMBus Timing Characteristics (continued)
T_A = –40°C to 85°C Typical Values at T_A = 25°C and V_(REG25) = 2.5 V (Unless Otherwise Noted)
PARAMETER
t_(TIMEOUT)
t_(LOW)
t_(HIGH)
t_(LOW:SEXT)
t_(LOW:MEXT)
Error signal/detect (see Figure 1)
Clock low period (see Figure 1)
Clock high period (see Figure 1)
Cumulative clock low slave extend time
Cumulative clock low master extend time (see
Figure 1)
t_f
Clock/data fall time
t_r
Clock/data rise time
TEST CONDITIONS
See ⁽¹⁾
See ⁽²⁾
See ⁽³⁾
See ⁽⁴⁾
See ⁽⁵⁾
See ⁽⁶⁾
MIN TYP MAX UNIT
25
35 µs
4.7
µs
4.0
50 µs
25 µs
10 µs
300 ns
1000 ns
(1) The bq20z75 times out when any clock low exceeds t_(TIMEOUT).
(2) t_(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z75 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t_(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t_(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time t_r = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time t_f = 0.9V_DD to (VILMAX – 0.15)
t_(LOW)
t_r
t_f
t_(HD:STA)
SCLK
SDATA
P
t_(HD:STA)
t_(HD:DAT)
t_(HIGH)
t_(SU:DAT)
t_(SU:STA)
t_(SU:STO)
t_(BUF)
S
S
P
Start
t_(LOW:SEXT)
SCLK_ACK(1)
t_(LOW:MEXT)
t_(LOW:MEXT)
Stop
SCLK_ACK(1)
t_(LOW:MEXT)
SCLK
SDATA
A. SCLK_ACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
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