TSB41LV02A Datasheet, PDF (1/50 Pages) Texas Instruments – IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

TSB41LV02A
IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER
D Fully Supports Provisions of IEEE
1394-1995 Standard for High-Performance
Serial Bus^† and the P1394a Supplement
D Fully Interoperable With FireWire™ and
i.LINK™ Implementation of IEEE Std 1394
D Fully Compliant With OpenHCI
Requirements
D Provides Two P1394a Fully Compliant
Cable Ports at 100/200/400 Megabits per
Second (Mbits/s)
D Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume
D Extended Resume Signaling for
Compatibility With Legacy DV Devices
D Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Pin, Link
Interface Disable via LPS, and Inactive
Ports Powered Down
D Ultra Low-Power Sleep Mode
D Node Power Class Information Signaling
for System Power Management
D Cable Power Presence Monitoring
D Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
SLLS400A – JANUARY 2000 – REVISED MAY 2000
D Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit and P1394a Features
D Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
D Interface to Link Layer Controller Supports
Low Cost TI Bus-holder Isolation and
Optional Annex J Electrical Isolation
D Interoperable With Link-Layer Controllers
Using 3.3-V and 5-V Supplies
D Interoperable With Other Physical Layers
(PHYs) Using 3.3-V and 5-V Supplies
D Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
D Incoming Data Resynchronized to Local
Clock
D Logic Performs System Initialization and
Arbitration Functions
D Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
D Separate Cable Bias (TPBIAS) for Each Port
D Single 3.3-V Supply Operation
D Meets Intel Mobile Power Guideline 2000
D Low Cost High Performance 64 Pin TQFP
(PAP) Thermally Enhanced Package
description
The TSB41LV02A provides the digital and analog transceiver functions needed to implement a two-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV02A is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
The TSB41LV02A requires only an external 24.576 MHz crystal as a reference. An external clock may be
provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates
the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock
signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock
signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization
of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops
operation of the PLL.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†Implements _{technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.}
i.LINK is a trademark of Sony Corporation.
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1