TMS320C6202 Datasheet, PDF (1/86 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204
FIXED-POINT DIGITAL SIGNAL PROCESSORS
D Highest Performance Fixed-Point Digital
Signal Processors (DSPs) TMS320C62x
– 5-, 4-, 3.33-ns Instruction Cycle Time
– 200-, 250-, 300-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1600, 2 000, 2 400 MIPS
D VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C62x CPU Core
– Eight Highly Independent Functional
Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
D Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
D On-Chip SRAM
– 1M-Bit (’C6204)
– 3M-Bit (’C6202/’C6202B)
– 7M-Bit (’C6203)
D 32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
– 52M-Byte Addressable External Memory
Space
D Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
SPRS104A – OCTOBER 1999 – REVISED MARCH 2000
D Flexible Phase-Locked-Loop (PLL) Clock
Generator
D 32-Bit Expansion Bus
– Glueless/Low-Glue Interface to Popular
PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous
Microprocessor Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs
and Asynchronous Peripherals
D Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral Interface (SPI)
Compatible (Motorola™)
D Two 32-Bit General-Purpose Timers
D IEEE-1149.1 (JTAG^†)
Boundary-Scan-Compatible
D 352-Pin BGA Package (GJL) (’02/02B/03)
D 384-Pin BGA Package (GLS) (’02/02B/03)
D 340-Pin BGA Package (GLW) (’C6204 only)
– Pin-Compatible With the GLS Package
Except Inner Row of Balls (Additional
Power and Ground Pins) are Removed^‡
D 0.18-µm/5-Level Metal Process (’6202 only)
0.15-µm/5-Level Metal Process (’02B/03/04)
– CMOS Technology
D 3.3-V I/Os, 1.8-V Internal (’C6202 only)
3.3-V I/Os, 1.5-V Internal (’C6202B/03/04)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
† _{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.}
‡ _{For more details, see the GLS/GLW BGA package bottom view.}
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright © 2000, Texas Instruments Incorporated
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