SN75LVDS83 Datasheet, PDF (1/15 Pages) Texas Instruments – FLATLINKE TRANSMITTER

SN75LVDS83
FLATLINK™ TRANSMITTER
SLLS271B – MARCH 1997 – REVISED NOVEMBER 1999
D 28:4 Data Channel Compression at up to
227.5 Million Bytes per Second Throughput
D Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D 28 Data Channels and Clock-In Low-Voltage
TTL
D 4 Data Channels and Clock-Out
DGG PACKAGE
(TOP VIEW)
V_{CC 1}
D5 ₂
D6 ₃
D7 4
GND 5
D8 6
56 ^D4
55 ^D3
54 ^D2
53 GND
52 D1
51 D0
Low-Voltage Differential
D9 7
50 D27
D Operates From a Single 3.3-V Supply With
250 mW (Typ)
D ESD Protection Exceeds 6 kV
D 5-V Tolerant Data Inputs
D Selectable Rising or Falling Edge-Triggered
Inputs
D Packaged in Thin Shrink Small-Outline
D10 8
V_CC 9
D11 10
D12 11
D13 12
GND 13
D14 14
D15 15
49 LVDSGND
48 Y0M
47 Y0P
46 Y1M
45 Y1P
44 LVDSV_CC
43 LVDSGND
42 Y2M
Package With 20-Mil Terminal Pitch
D Consumes Less Than 1 mW When Disabled
D Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
D No External Components Required for PLL
D Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D Improved Replacement for the DS90C581
D16 16
CLKSEL 17
D17 18
D18 19
D19 20
GND 21
D20 22
D21 ²³
D22 ²⁴
41 Y2P
40 CLKOUTM
39 CLKOUTP
38 Y3M
37 Y3P
36 LVDSGND
35 PLLGND
34 _PLLVCC
33 _PLLGND
description
The SN75LVDS83 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
D23 ²⁵
V_CC ²⁶
D24 ²⁷
D25 ²⁸
32 _SHTDN
31 _CLKIN
30 _D26
29 _GND
7× clock synthesizer, and five low-voltage
differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of
single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors
for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit
links with the SN75LVDS86 receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)
terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in
7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS
output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all
internal registers to a low level.
The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a registered trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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