SN74GTL16616_06 Datasheet, PDF (1/14 Pages) Texas Instruments – 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS

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SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
SCBS481H – JUNE 1994 – REVISED APRIL 2005
FEATURES
• Member of the Texas Instruments Widebus™
Family
• UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enabled Modes
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• GTL Buffered CLKAB Signal (CLKOUT)
• Translates Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
• Supports Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
• Equivalent to '16601 Function
• I_off Supports Partial-Power-Down Mode
Operation
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
• Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
DGG OR DL PACKAGE
(TOP VIEW)
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
V_CC (3.3 V) 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V_CC (3.3 V) 22
A16 23
A17 24
GND 25
CLKIN 26
OEBA 27
LEBA 28
56 CEAB
55 CLKAB
54 B1
53 GND
52 B2
51 B3
50 V_CC (5 V)
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 V_REF
34 B16
33 B17
32 GND
31 CLKOUT
30 CLKBA
29 CEBA
DESCRIPTION/ORDERING INFORMATION
The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked,
and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for
a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic
levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane
operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing
(<1 V), reduced input threshold levels, and OEC™ circuitry.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
SSOP – DL
Tube
Tape and reel
SN74GTL16616DL
SN74GTL16616DLR
TSSOP – DGG Tape and reel
SN74GTL16616DGGR
TOP-SIDE MARKING
GTL16616
GTL16616
GTL16616
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2005, Texas Instruments Incorporated