SN74ALVCH32501 Datasheet, PDF (1/11 Pages) Texas Instruments – 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

D Member of the Texas Instruments
Widebus ™ Family
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D UBT ™ (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
This 36-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.
This device can be used as two 18-bit transceivers or one 36-bit transceiver. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When
OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or power down, OEBA should be tied to V_CC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH32501 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE†
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↑
L
L
H
L
↑
H
H
H
L
H
X
B0‡
H
L
L
X
B0§
† _{A-to-B data flow is shown; B-to-A flow is similar but}
uses OEBA, LEBA, and CLKBA.
‡ _{Output level before the indicated steady-state input}
conditions were established, provided that CLKAB
was high before LEAB went low
§ _{Output level before the indicated steady-state input}
conditions were established
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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