SN74ALVCH162260 Datasheet, PDF (1/11 Pages) Texas Instruments – 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS570H – MARCH 1996 – REVISED JUNE 1999
D Member of the Texas Instruments
Widebus ™ Family
D EPIC ™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D B-Port Outputs Have Equivalent 26-Ω
Series Resistors, So No External Resistors
Are Required
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Thin-Shrink
Small-Outline (DGG) and Plastic Shrink
Small-Outline (DL) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
This 12-bit to 24-bit multiplexed D-type latch is
designed for 1.65-V to 3.6-V_CC operation.
The SN74ALVCH162260 is used in applications
in which two separate data paths must be
multiplexed onto, or demultiplexed from, a single
data path. Typical applications include
multiplexing and/or demultiplexing address and
data information in microprocessor or
bus-interface applications. This device also is
useful in memory-interleaving applications.
DGG OR DL PACKAGE
(TOP VIEW)
OEA 1
LE1B 2
2B3 3
GND 4
2B2 5
2B1 6
V_CC 7
A1 8
A2 9
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
V_CC 22
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
56 OE2B
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
50 V_CC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 V_CC
34 1B6
33 1B5
32 GND
31 1B4
30 LEA1B
29 OE1B
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B
control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
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