SN74ALVC7803 Datasheet, PDF (1/14 Pages) Texas Instruments – 512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SN74ALVC7803
512 × 18
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SDAS274 – JANUARY 1995
• Operates at 3-V to 3.6-V V_CC
• Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
• Read and Write Operations Synchronized to
Independent System Clocks
• Low-Power Advanced CMOS Technology
• Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
• Bidirectional Configuration and Width
Expansion Without Additional Logic
• Input-Ready Flag Synchronized to Write
Clock
• Output-Ready Flag Synchronized to Read
Clock
• Fast Access Times of 13 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
• Data Rates From 0 to 50 MHz
• Pin Compatible With SN74ACT7803
• Packaged in Shrink Small-Outline 300-mil
Package (DL) Using 25-mil Center-to-Center
Lead Spacing
description
The SN74ALVC7803 FIFO is suited for buffering
asynchronous data paths at 50-MHz clock rates
and 13-ns access times and is designed for 3-V to
3.6-V V_CC operation. The 56-pin shrink small-
outline (DL) package offers greatly reduced board
space over DIP, PLCC, and conventional SOIC
packages. Two devices can be configured for
bidirectional data buffering without additional
logic.
DL PACKAGE
(TOP VIEW)
RESET 1
D17 2
D16 3
D15 4
D14 5
D13 6
D12 7
D11 8
D10 9
V_CC 10
D9 11
D8 12
GND 13
D7 14
D6 15
D5 16
D4 17
D3 18
D2 19
D1 20
D0 21
HF 22
PEN 23
AF/AE 24
WRTCLK 25
WRTEN2 26
WRTEN1 27
IR 28
56 OE1
55 Q17
54 Q16
53 Q15
52 GND
51 Q14
50 V_CC
49 Q13
48 Q12
47 Q11
46 Q10
45 Q9
44 GND
43 Q8
42 Q7
41 Q6
40 Q5
39 V_CC
38 Q4
37 Q3
36 Q2
35 GND
34 Q1
33 Q0
32 RDCLK
31 RDEN
30 OE2
29 OR
The write clock (WRTCLK) and read clock (RDCLK) should be free running and can be asynchronous or
coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low,
and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and
OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output
buffer regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the
output buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes
the IR, OR, and half-full (HF) flags low and the almost-full /almost-empty (AF/AE) flag high. The FIFO must be
reset upon power up.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
1