SN54GTL16612 Datasheet, PDF (1/13 Pages) Texas Instruments – 18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS

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SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K – JUNE 1994 – REVISED JULY 2005
FEATURES
• Members of Texas Instruments Widebus™
Family
• UBT™ Transceivers Combine D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enabled Modes
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
• Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
• Identical to '16601 Function
• I_off Supports Partial-Power-Down Mode
Operation
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
• Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
• Latch-Up Performance Exceeds 500 mA Per
JESD 17
SN54GTL16612 . . . WD PACKAGE
SN74GTL16612 . . . DGG OR DL PACKAGE
(TOP VIEW)
OEAB 1
LEAB 2
A1 3
GND 4
A2 5
A3 6
V_CC (3.3 V) 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V_CC (3.3 V) 22
A16 23
A17 24
GND 25
A18 26
OEBA 27
LEBA 28
56 CEAB
55 CLKAB
54 B1
53 GND
52 B2
51 B3
50 V_CC (5 V)
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 V_REF
34 B16
33 B17
32 GND
31 B18
30 CLKBA
29 CEBA
DESCRIPTION/ORDERING INFORMATION
The 'GTL16612 devices are 18-bit UBT™ transceivers that provide LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for
transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The
devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at
GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced
input threshold levels, and OEC™ circuitry.
The user has the flexibility of using these devices at either GTL (V_TT = 1.2 V and V_REF = 0.8 V) or the preferred
higher noise margin GTL+ (V_TT = 1.5 V and V_REF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V_REF is the reference input voltage for the B port.
V_CC (5 V) supplies the internal and GTL circuitry while V_CC (3.3 V) supplies the LVTTL output buffers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.